DigitalLogicDesign
Question 1 
1111 1111 1110 0100  
1111 1111 0001 1100  
0000 0000 1110 0100  
1000 0000 1110 0100 
1’s complement = 1111 1111 1110 0011
2’s complement = 1’s complement + 1
2’s complement = 1111 1111 1110 0100
= (28)
Question 2 
Two numbers are chosen independently and uniformly at random from the set {1, 2, ..., 13}. The probability (rounded off to 3 decimal places) that their 4bit (unsigned) binary representations have the same most significant bit is ______.
0.502  
0.461  
0.402  
0.561 
1  0001
2  0010
3  0011
4  0100
5  0101
6  0110
7  0111
8  1000
9  1001
10  1010
11  1011
12  1100
13  1101
The probability that their 4bit binary representations have the same most significant bit is
= P(MSB is 0) + P(MSB is 1)
= (7×7)/(13×13) + (6×6)/(13×13)
= (49+36)/169
= 85/169
= 0.502
Question 3 
Consider Z = X  Y, where X, Y and Z are all in signmagnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:
n bits  
n + 2 bits  
n  1 bits  
n + 1 bits 
To store overflow/carry bit there should be extra space to accommodate it.
Hence, Z should be n+1 bits.
Question 4 
(x + y) ⊕ z = x ⊕ (y + z)  
(x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)  
x ⊕ y = x + y, if xy = 0  
x ⊕ y = (xy + x'y')' 
(x+y) ⊕ z = (1+1)⊕ 0 = 1 ⊕ 0 = 1
x ⊕ (y+z) = 1⊕(1+0) = 1 ⊕ 1 = 0
So,
(x+y) ⊕ z ≠ x ⊕ (y+z)
Question 5 
What is the minimum number of 2input NOR gates required to implement a 4variable function function expressed in sumofminterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available.
2  
4  
7  
1  
3(Option not given) 
Question 6 
Consider three 4variable functions f_{1}, f_{2} and f_{3}, which are expressed in sumofminterms as
f_{1} = Σ(0, 2, 5, 8, 14), f_{2} = Σ(2, 3, 6, 8, 14, 15), f_{3} = Σ(2, 7, 11, 14)
For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:
Σ (2, 14)  
Σ (7, 8, 11)  
Σ (2, 7, 8, 11, 14)  
Σ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15) 
f3 = ∑(2,7,11,14)
f1*f2 ⊕ f3 = ∑(2,8,14) ⊕ ∑(2,7,11,14)
= ∑(8,7,11) (Note: Choose the terms which are not common)
Question 7 
5 
A 2^{5}x1 Multiplexer with 5 select lines selects one of the 32(= 2^{5} )registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 8 
1034 
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 9 
Which one of the following minterm lists represents the circuit given above?
Z=Σ(0,1,3,7)
 
Z=Σ(2,4,5,6,7)
 
Z=Σ(1,4,5,6,7)  
Z=Σ(2,3,5)

Convert a+b’c into canonical form which is sum of minterms.
a+b’c = a(b+b’)(c+c’)+ (a+a’)b’c
= abc + abc’ + ab’c + ab’c’ + ab’c + a’b’c
=Σ(7,6,5,4,1)
Question 10 
If R3 = R1/R2, what is the value stored in R3?
0x40800000
 
0x83400000
 
0xC8500000
 
0xC0800000

Question 11 
Question 12 
Consider the sequential circuit shown in the figure, where both flipflops used are positive edgetriggered D flipflops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2  
3  
4  
5 
Now lets draw characteristic table,
D_{1} = Q_{0}
D_{0} = in
Question 13 
Consider the unsigned 8bit fixed point binary number representation below,

b_{7}b_{6}b_{5}b_{4}b_{3} ⋅ b_{2}b_{1}b_{0}
where the position of the binary point is between b_{3} and b_{2} . Assume b_{7} is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001
Which one of the following statements is true?
None of (i), (ii), (iii), (iv) can be exactly represented
 
Only (ii) cannot be exactly represented
 
Only (iii) and (iv) cannot be exactly represented
 
Only (i) and (ii) cannot be exactly represented

= 16 + 8 + 4 + 2 + 1 + 0.5
= (31.5)_{10}
(ii) (0.875)_{10} = (00000.111)_{2}
= 2^{1} + 2^{2} + 2^{3}
= 0.5 + 0.25 + 0.125
= (0.875)_{10}
(iii) (12.100)_{10}
It is not possible to represent (12.100)_{10}
(iv) (3.001)_{10} It is not possible to represent (3.001)_{10}
Question 14 
Consider the minterm list form of a Boolean function F given below.
 F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)
Here, m denotes a minterm and d denotes a don’t care term. The number of essential prime implicants of the function F is _______ .
3  
4  
5  
6 
There are 3 prime implicant i.e., P’QS, Q’S’ and PQ’ and all are essential.
Because 0 and 2 are correct by only Q’S’, 5 and 7 are covered by only P’QS and 8 and 9 are covered by only PQ’.
Question 15 
2^{f} to 2^{i}  
2^{f} to (2^{i}  2^{f})  
0 to 2^{i}  
0 to (2^{i}  2^{f }) 
Number of bits in fraction part → fbits
Number of bits in integer part → (n – f) bits
Minimum value:
000…0.000…0 = 0
Maximum value:
= (2^{ nf }  1) + (1  2 ^{f}
= (2^{nf}  2 ^{f})
= (2^{i}  2 ^{ f })
Question 16 
When two 8bit numbers A_{7}...A_{0} and B_{7}...B_{0} in 2’s complement representation (with A_{0} and B_{0} as the least significant bits) are added using a ripplecarry adder, the sum bits obtained are S_{7}...S_{0} and the carry bits are C_{7}...C_{0}. An overflow is said to have occurred if
the carry bit C_{7} is 1  
all the carry bits (C_{7},…,C_{0}) are 1  
i.e., A_{7} = B_{7}
⇾ Overflow can be detected by checking carry into the sign bits (C_{in}) and carry out of the sign bits (C_{out}).
⇾ Overflow occurs iff A_{7} = B_{7} and C_{in} ≠ C_{out}
These conditions are equivalent to
Consider
Here A_{7} = B_{7} = 1 and S_{7} = 0
This happens only if C_{in} = 0
Carry out C_{out}=1 when
Similarly, in case of
C_{in}=1 and C_{out} will be 0.
Question 17 
Consider the Karnaugh map given below, where X represents “don’t care” and blank represents 0.
Assume for all inputs , the respective complements are also available. The above logic is implemented using 2input NOR gates only. The minimum number of gates required is _________.
1  
2  
3  
4 
As all variables and their complements are available we can implement the function with only one NOR Gate.
Question 18 
Consider a combination of T and D flipflops connected as shown below. The output of the D flipflop is connected to the input of the T flipflop and the output of the T flipflop is connected to the input of the D flipflop.
Initially, both Q_{0} and Q_{1} are set to 1 (before the 1^{st} clock cycle). The outputs
Question 19 
The representation of the value of a 16bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is
136251  
736251  
571247  
136252 
Each hexadecimal digit is equal to a 4bit binary number. So convert
X = (BCA9)_{16} to binary
Divide the binary data into groups 3 bits each because each octal digit is represented by 3bit binary number.
X = (001 011 110 010 101 001)_{2}
Note: Two zeroes added at host significant position to make number bits of a multiple of 3 (16 + 2 = 18)
X = (136251)_{8}
Question 20 
Given the following binary number in 32bit (single precision) IEEE754 format:
The decimal value closest to this floatingpoint number is
1.45 × 10^{1}  
1.45 × 10^{1}  
2.27 × 10^{1}  
2.27 × 10^{1} 
For singleprecision floatingpoint representation decimal value is equal to (1)^{5} × 1.M × 2^{(E127)}
S = 0
E = (01111100)_{2} = (124).
So E – 127 =  3
1.M = 1.11011010…0
= 2^{0} + 2^{(1)} + 2^{(1)} + 2^{(4)} + 2^{(5)} + 2^{(7)}
= 1+0.5+0.25+0.06+0.03+0.007
≈ 1.847
(1)^{5} × 1.M × 2^{(E127)}
= 1^{0} × 1.847 × 2^{3}
≈ 0.231
≈ 2.3 × 10^{1}
Question 21 
Consider a quadratic equation x^{2}  13x + 36 = 0 with coefficients in a base b. The solutions of this equation in the same base b are x = 5 and x = 6. Then b=________.
8  
9  
10  
11 
Generally if a, b are roots.
(x  a)(x  b) = 0
x^{2}  (a + b)x + ab = 0
Given that x=5, x=6 are roots of (1)
So, a + b = 13
ab=36 (with same base ‘b’)
i.e., (5)_{b} + (6)_{b} = (13)_{b}
Convert them into decimal value
5_{b} = 5_{10}
6_{10} = 6_{10}
13_{b} = b+3
11 = b+3
b = 8
Now check with ab = 36
5_{b} × 6_{b} = 36_{b}
Convert them into decimals
5_{b} × 6_{b} = (b×3) + 6_{10}
30 = b × 3 + 6
24 = b × 3
b = 8
∴ The required base = 8
Question 22 
If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?
wx + w(x + y) + x(x + y) = x + wy  
(w + y)(wxy + wyz) = wxy + wyz 
wx + w(x + y) + x(x + y)
= (wx + wx) + wy + (x + xy)
= wx + wy + x(1 + y)
= wx + wy + x
= (w + 1)x + wy
= x + wy
OptionB:
OptionC:
OptionD:
(w + y)(wxy + wyz) = wxy + wyz + wxy + wyz = wxy + wyz
Question 23 
Given f(w,x,y,z) = Σ_{m}(0,1,2,3,7,8,10) + Σ_{d}(5,6,11,15), where d represents the don’tcare condition in Karnaugh maps. Which of the following is a minimum productofsums (POS) form of f(w,x,y,z)?
KMap for the function f is
Consider maxterms in Kmap to represent function in productofsums (POS) form
f(w,x,y,z) = (w' + z')(x' + z)
Question 24 
Consider a binary code that consists of only four valid code words as given below:
Let the minimum Hamming distance of the code be p and the maximum number of erroneous bits that can be corrected by the code be q. Then the values of p and q are
p=3 and q=1  
p=3 and q=2  
p=4 and q=1  
p=4 and q=2 
Minimum Distance = p = 3
Error bits that can be corrected = (p1)/2 = (31)/2 = 1
∴ p=3 and q=1
Question 25 
The next state table of a 2bit saturating upcounter is given below.
The counter is built as a synchronous sequential circuit using T flipflops. The expressions for T_{1} and T_{0} are
By using above excitation table,
Question 26 
ExOR satisfies all the properties. Hence,
Question 27 
The 16bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________.
11  
12  
13  
14 
It is a negative number because MSB is 1.
Magnitude of 1111 1111 1111 0101 is 2’s complement of 1111 1111 1111 0101.
1111 1111 1111 0101
0000 0000 0000 1010 : 1’s Complement
0000 0000 0000 1011 : 2’s complement
= (11)_{10}
Hence, 1111 1111 1111 0101 = 11
Question 28 
We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK ﬂipﬂops required to implement this counter is __________.
4  
5  
6  
7 
There are 3 transitions from 0.
Hence ⌈log_{2}^{3}⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 29 
Consider the two cascaded 2to1 multiplexers as shown in the ﬁgure.
The minimal sum of products form of the output X is
Now
Question 30 
Consider a carry lookahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is __________.
Θ(1)  
Θ(log(n))  
Θ(√n)  
Θ(n) 
Where n is number of bits added
and k is fanin of the gates.
As we are adding nbit numbers and fanin is at most 2,
the solution is θ(log_{2} (n)).
Question 31 
Consider an eightbit ripplecarry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________.
1  
2  
3  
4 
If we do 2's complement of 1 = 0000 0001, we get 1 = "1111 1111"
So, if B = 1, every carry bit is 1.
Question 32 
Let, x_{1}⊕x_{2}⊕x_{3}⊕x_{4} = 0 where x_{1}, x_{2}, x_{3}, x_{4} are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE?
x_{1}x_{2}x_{3}x_{4} = 0  
x_{1}x_{3}+x_{2} = 0  
x_{1} + x_{2} + x_{3} + x_{4} = 0 
x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4} = 0 (1)
A) x_{1}x_{2}x_{3} x_{4} = 0
Put x_{1} = 1, x_{2} = 1, x_{3} = 1, x_{4} = 1
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 1 ⊕ 1 = 0
But,
x_{1}x_{2}x_{3} x_{4} ≠ 0
So, false.
B) x_{1}x_{3} + x_{2} = 0
Put x_{1} = 1, x_{2} = 1, x_{3} = 0 , x_{4} = 0
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 0 ⊕ 0 = 0
But,
x_{1}x_{3} + x_{2} ≠ 0
So, false.
D) x_{1} + x_{2} + x_{3} + x_{4} = 0
Let x_{1}=1, x_{2}=1, x_{3}=0, x_{4}=0
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 0 ⊕ 0 = 0
But,
x_{1} + x_{2} + x_{3} + x_{4} ≠ 0
So, false.
(i) True.
Question 33 
Let X be the number of distinct 16bit integers in 2’s complement representation. Let Y be the number of distinct 16bit integers in sign magnitude representation.
Then XY is _________.
1  
2  
3  
4 
Since range is  2^{15} to 2^{15}  1
Y = 2^{16}  1
Here, +0 and 0 are represented separately.
X  Y = 2^{16}  (2^{16}  1)
= 1
Question 34 
0, 1, 3, 7, 15, 14, 12, 8, 0  
0, 1, 3, 5, 7, 9, 11, 13, 15, 0  
0, 2, 4, 6, 8, 10, 12, 14, 0  
0, 8, 12, 14, 15, 7, 3, 1, 0 
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 35 
Both commutative and associative  
Commutative but not associative  
Not commutative but associative  
Neither commutative nor associative 
Question 36 
A positive edgetriggered D flipflop is connected to a positive edgetriggered JK flipflop as follows. The Q output of the D flipflop is connected to both the J and K inputs of the JK flipflop, while the Q output of the JK flipflop is connected to the input of the D flipflop. Initially, the output of the D flipflop is set to logic one and the output of the JK flipflop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flipflop when the flipflops are connected to a freerunning common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the stateholding mode of the JK flipflop. Both the flipflops have nonzero propagation delays.
0110110...  
0100100...  
011101110...  
011001100...

The characteristic equations are
Q_{DN}=D=Q_{JK}
The state table and state transition diagram are as follows:
Consider Q_{D}Q_{JK}=10 as initial state because in the options Q_{JK}=0 is the initial state of JK flipflop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 37 
2  
3  
4  
5 
00
00
01
01
10
10
11
11
In the above sequence two flipflop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
Now and every count is unique, occuring only once.
So finally 3flip flops is required.
Question 38 
1  
2  
3  
4 
[D' + AB' + A'C + AC'D + A'C'D]'
[D' + AB' + A'C + C'D (A + A')']' (since A+A' = 1)
[AB' + A'C + (D' + C') (D' + D)]' (since D' + D =1)
[AB' + A'C + D' + C']'
[AB' + (A' + C') (C + C') + D']'
[AB' + A' + C' + D']'
[(A + A') (A' + B') + C' + D']'
[A' + B' + C' + D']'
Apply demorgan's law,
ABCD
Question 39 
19.1  
19.2  
18.1  
18.2 
Here, each Full Adder is taking 4.8 microseconds. Given adder is a 4 Bit Ripple Carry Adder. So it takes 4* 4.8= 19.2 microseconds.
Question 40 
3  
4  
2  
1 
Total 3 prime implicants are there.
Question 41 
F(P, Q, R, S) = PQ + P'QR + P'QR'SThe minimal sumofproducts form of F is
= Q(P+P’R) + P’QR’S
= Q(P+R) + P’QR’S
=QP + QR + P’QR’S
= QP + Q(R + P’R’S)
= QP + Q( R + P’S)
= QP + QR + QP’S
= Q(P+P’S) + QR
= Q(P+S)+ QR
= QP + QS + QR
Question 42 
312/20 = 13.1
5  
6  
7  
8 
(3r^{2} + r + 2) / 2r= (r+3+1/r)
(3r^{2} + r + 2) / 2r= (r^{2}+3r+1) / r
(3r^{2} + r + 2) = (2r^{2}+6r+2)
r^{2} 5r = 0
Therefor r = 5
Question 43 
= P’Q + PQ’R + PQR’
= Q(P’ + P R’) + PQ’R
= Q(P’ + R’) + PQ’R
= P’Q + QR’ + PQ’R
Question 44 
2^{n}  
2^{(n1)}  
2^{(2n )}  
2^{(2(n1) )} 
Number of mutually exclusive pairs of minterms = 2^{n1}.
There are 2 choices for each pair i.e., we can choose one of the two minterms from each pair of minterms for the function.
Therefore number of functions = 2 x 2 x …. 2^{n1} times.
= 2^{(2(n1) ) }
Question 45 
kbit binary up counter.  
kbit binary down counter.  
kbit ring counter.  
kbit Johnson counter. 
A n x 2^{n} decoder is a combinational circuit with only one output line has one and all others (2^{n}1) have zeros.
A nbit binary Counter produces outputs from 0 to 2^{n} i.e 000...00 to 111...11 and repeats.
The n x 2^{n} Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2^{n}  bit ring counter.
Question 46 
3  
5  
6  
7 
(123)_{5} = (x8)_{y}
In R.H.S. since y is base so y should be greater than x and 8, i.e.,
y > x
y > 8
Now, to solve let's change all the above bases number into base 10 number,
5^{2} × 1 +2 × 5 + 3 = y × x + 8
38 = xy + 8
xy = 30
⇒ yx = 30
So the possible combinations are
(1,30), (2,15), (3,10), (5,6)
But we will reject (5,6) because it violates the condition (y > 8).
So, total solutions possible is 3.
Question 48 
Full adder  
Priority encoder  
Multiplexor  
Flipflop 
x is the select line, I_{0} is 'b' and I_{1} is a.
The output line, y = xa + x’b
Question 49 
001, 010, 011  
111, 110, 101  
100, 110, 111  
100, 011, 001 
Question 50 
P+Q  
P⨁Q  
⊕ is associative i.e P ⊕ (Q ⊕ R) = (P⊕Q) ⊕ R.
P ⊕ P = 0, 1 ⊕ P = P’ and 0 ⊕ Q = Q
(1 ⊕ P ) ⊕ ((P ⊕ Q) ⊕ (P ⊕ Q)) ⊕ (Q ⊕ 0)
= P’⊕ (0) ⊕ Q
= P’ ⊕ Q
= (P ⊕ Q)’
Question 51 
256  
128  
127  
0 
The smallest 8bit 2’s complement number is 1000 0000.
MSB is 1. So it is a negative number.
To know the magnitude again take 2’s complement of 1000 0000.
1000 0000
0111 1111 ← 1’s complement
1000 0000 ← 2’s complement (1’s complement +1)
= 128
128 is 1000 0000 in 2’s complement representation.
Question 52 
Priority encoder  
Decoder  
Multiplexer  
Demultiplexer 
Question 53 
xy+x'y'  
x⊕y'  
x'⊕y  
x'⊕y' 
x’ ⊕ y’ = xy’ + x’y = x⊕y. Hence option D is correct.
Question 54 
X  
X + Y  
X ⊕ Y  
Y 
Question 55 
fraction bits of 000…000 and exponent value of 0  
fraction bits of 000…000 and exponent value of −1  
fraction bits of 100…000 and exponent value of 0  
no exact representation 
So, value of the exponent = 1
and
fraction is 000…000 (Implicit representation)
Question 56 
64 bits  
128 bits  
1 Kbits  
2 Kbits 
Hence option D is the answer.
Question 59 
9  
8  
512  
258 
The max Mod values is 2n.
So 2^{n} ≥ 258 ⇒ n = 9
Question 60 
Question 61 
3  
4  
5  
6 
So total no. of distinct output (states) are 4.
Question 62 
000  
001  
010  
011 
So, after 010 it moves to 011.
Question 63 
m_{2}+m_{4}+m_{6}+m_{7}  
m_{0}+m_{1}+m_{3}+m_{5}  
m_{0}+m_{1}+m_{6}+m_{7}  
m_{2}+m_{3}+m_{4}+m_{5} 
= PQR + PQR' + PQR' + P'QR' + PQR' + PQ'R'
= PQR + PQR' + P'QR' + PQ'R'
=m_{7} + m_{6} + m_{2} + m_{4}
Question 64 
100 nanoseconds  
100*2^{10} nanoseconds  
100*2^{20} nanoseconds  
3200*2^{20} nanoseconds 
Required capacity = 4MB
Number of chips needed = 4M*8 bits / 1M x 1bit = 32 (1M x 1bit)/(1M x 1bit) = 32
Irrespective of the number of chips, all chips can be refreshed in parallel.
And all the cells in a row are refreshed in parallel too. So, the total time for refresh will be number of rows times the refresh time of one row.
Here we have 1K rows in a chip and refresh time of single row is 100ns.
So total time required =1K×100
=100 ×2^{10} nanoseconds
Question 65 
(C3D8)_{16}  
(187B)_{16}  
(F878)_{16}  
(987B)_{16} 
(F87B)_{16}=(1111 1000 0111 1011)_{2}. (It is a negative number which is in 2's complement form)
P=1111 1000 0111 1011 (2's complement form)
8 * P = 2^{3}* P= 1100 0011 1101 1000. ( NOTE: Left shift k times is equivalent to Multiplication by 2^{k})
Hence, 1100 0011 1101 1000 is 2's complement representation of 8P.
1100 0011 1101 1000 = (C3D8)_{16}.
Question 66 
P⊕Q⊕R
 
P+Q+R  
= (P’Q’ + PQ)R + (P’Q+PQ’)R’
= (P⊕Q)’ R + (P⊕Q)R’
= (P⊕Q⊕R)
Question 67 
= (P’Q’ + Q’R’)( P’R’ + Q’R’)
= (P’Q’P’R’ + P’Q’Q’R’ + Q’R’P’R’ + Q’R’Q’R’)
= (P’Q’R’ + P’Q’R’ + P’Q’R’ + Q’R’)
= (P’Q’R’ + Q’R’)
= (Q’R’)
= (Q+R)’
Question 68 
11, 10, 01, 00
 
10, 11, 01, 00  
10, 00, 01, 11  
11, 10, 00, 01

The next four values of Q_{1}Q_{0} are 11, 10, 01, 00.
Question 69 
(1217)_{16}
 
(028F)_{16}
 
(2297)_{10}
 
(0B17)_{16} 
Divide the bits into groups, each containing 4 bits.
=(0010 1000 1111)_{2}
=(28F)_{16}
Question 70 
2  
3  
4  
5 
AB+C
= (A+C)(B+C) ← Distribution of + over
= ((A+C)’+(B+C)’)’
1st NOR (A+C)’. Let X = (A+C)’
2nd NOR (B+C)’. Let Y = (B+C)’
3rd NOR (X+Y)’
Question 71 
8  
32  
64  
128 
Needed memory capacity = 256Kbytes = 256K*8 bits
Number of chips needed = 256K*8 / 32K×1= 64
Question 72 
the normalized value 2^{127}  
the normalized value 2^{126}
 
the normalized value +0
 
the special value +0

Question 73 
Question 74 
decimal 10
 
decimal 11
 
decimal 10 and 11  
any value >2

Any value of r will satisfy the above equation. But the radix should be greater than 2 because the 121 has 2. So r >2 is correct.
Question 75 
Question 76 
EXNOR  
implication, negation  
OR, negation  
NAND 
→ NOR and NAND are the functionally complete logic gates, OR, AND, NOT only logic gate can be implemented by using them.
→ And (Implication, Negation) is also functionally complete.
Question 77 
10  
13  
26  
None of these 
Exponent bits  10000011
Exponent can be added with 127 bias in IEEE single precision format then outval exponent
= 10000011  127
= 131  127
= 4
→ In IEEE format, an implied 1 is before mantissa, and hence the outval number is
→ 1.101 × 2^{4} = (11010)_{2} = 26
Question 78 
independent of one variable  
independent of two variables  
independent of three variable  
dependent on all the variables 
Independent of one variable '0'.
Question 79 
xz+x’z’  
xz’+x’z  
x’y’+yz  
xy+y’z’ 
= (x’z’ + xz)’
= x’z + xz’
Question 80 
1, 1, 0  
1, 0, 0  
0, 1, 0  
1, 0, 1 
Carry flag = 1
Overflow flag = 0
Sign bit = 0 (MSB bit is 0)
Overflow flag:
In computer processors, the overflow flag is usually a single bit in a system status register used to indicate when an arithmetic overflow has occurred in an operation.
Question 81 
(x⊕y)’ and x’⊕y’  
(x⊕y)’ and x⊕y  
x⊕y and (x⊕y)’  
x⊕y and x⊕y 
Excitation table of JK:
Question 82 
6  
8  
10  
12 
Now we have some values defined for pair of bits in Booth’s Algorithm,
00 → 0
11 → 0
01 → 1
10 → 1
Now after adding 0 to the LSB of the multiplier, start traversing from left to right and accordingly put the values defined above.
Hence, total 8 additions / subtractions required.
Question 83 
n^{2}  
2^{n}  
2^{2n}  
2^{n2} 
Number of variables= n
Number of input combinations is 2^{n}.
Each “boolean” function has two possible outputs i.e 0 and 1.
Number of boolean functions possible is 2^{2n}.
Formula: The number of mary functions possible with n kary variables is m^{kn}.
Question 84 
7  
8  
9  
10 
So, we can say that
8 lines covered by  1 decoder
1 line covered by  1/8 decoder
64 lines covered by  64/8 = 8 decoders
8 lines covered by  8/8 = 1 decoder
Hence total no. of decoder needed is,
8 + 1 = 9 decoders.
Question 85 
independent of one variable.  
independent of two variables.
 
independent of three variables.  
dependent on all the variables.

w and y are not needed to represent the function f. So f is independent of two variables.
Question 86 
x'y'z' + w'xy' + wy'z + xz 

w'y'z' + wx'y' + xz 

R 
w'y'z' + wx'y' + xyz + xy'z 
S 
x'y'z' + wx'y' + w'y 
P only
 
Q and S
 
R and S  
S only

(P), (Q), (R) cover all the minterms and are equivalent to f(w,x,y,z) = Σ(0,4,5,7,8,9,13,15).
(S) covers the minterms m_{0}, m_{8}, m_{9}, m_{2}, m_{3}, m_{6}, m_{7}.
(S) is not covering the minterms m_{4}, m_{5}, m_{13}, m_{15}.
Question 87 
Consider the following expressions P, Q and R. P: X = Y⋆Z Q: Y = X⋆Z R: X⋆Y⋆Z=1Which of the following is TRUE?
Only P and Q are valid.  
Only Q and R are valid.
 
Only P and R are valid.  
All P, Q, R are valid. 
=Y(XY + X’Y’) + Y’(XY+X’Y’)’
=XY+Y’(X ⊕ Y)
=XY+Y’(XY’+X’Y)
=XY+XY’
=X(Y+Y’) =X
Q: X*Z = (XZ + X’Z’)
= X(XY + X’Y’) + X’(XY + X’Y’)’
=XY+X’(X’Y+XY’)
=XY+X’Y
=(X+X’)Y = Y
R: X* Y*Z
= X*X Since P: Y*Z= X
=XX + X’X’
= 1
Question 88 
2^{n} line to 1 line  
2^{n+1} line to 1 line
 
2^{n1} line to 1 line
 
2^{n2} line to 1 line 
A 2^{n} X 1 multiplexer can implement any function of n variables. As n variables are given to select lines, so that true and complement forms of all variables get generated inside the MUX.
As one inverter is available, we can generate complement of one variable outside of the Multiplexer. And remaining (n1) variables are given to select lines. With this we have true and complement form of all n variables.
So, the answer is 2^{n1} X 1 MUX.
Question 89 
P_{i} = A_{i} ⨁ B_{i} and G_{i} = A_{i}B_{i}The expressions for the sum bit S_{i} and the carry bit C_{i+1} of the lookahead carry adder are given by:
S_{i} = P_{i} ⨁ C_{i} and C_{i+1} = G_{i} + P_{i}C_{i} , where C_{0} is the input carry.Consider a twolevel logic implementation of the lookahead carry generator. Assume that all P_{i} and G_{i} are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the lookahead carry generator for a 4bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:
6, 3  
10, 4
 
6, 4  
10, 5

Question 90 
0, 3, 4  
0, 3, 4, 5
 
0, 1, 2, 3, 4
 
0, 1, 2, 3, 4, 5

Here, initial state is 0000. It goes through 0001,0010,0011,0100 and 0101. When the state is 5(0101) it immediately resets to initial state 0. Here, state 5 is not considered as valid state.
So valid states are 0,1,2,3, and 4 and hence it is a Mod5 counter.
Question 91 
For any formula, there is a truth assignment for which at least half the clauses evaluate to true.
 
For any formula, there is a truth assignment for which all the clauses evaluate to true.
 
There is a formula such that for each truth assignment, at most onefourth of the clauses evaluate to true.
 
None of the above.

Formula: a ∧ b
Truth table:
Conjunctive normal form : (a ∨ b) ∧ (a ∨ ~b) ∧ (~a ∨ b)
Similarly,
For n=1TRUE=1, FALSE=1 (1/2 ARE TRUE)
For n=2TRUE=3, FALSE=1 (3/4 ARE TRUE)
For n=3TRUE=7, FALSE=1 (7/8 ARE TRUE)
(12^{n}) are TRUE.
Looking at options,
Question 92 
11, 00  
01, 10  
10, 01  
00, 11 
So, 00 input cause indeterminate state which may lead to oscillation.
Question 93 
X1 = b, X2 = 0, X3 = a  
X1 = b, X2 = 1, X3 = b  
X1 = a, X2 = b, X3 = 1  
X1 = a, X2 = 0, X3 = b

If we put
X1 = b
X2 = 0
X3 = a
Then we get,
F = ab
Question 94 
1  
a’ + b’ + c’ + d’  
a’ + b + c’ + d’  
a’ + b’ + c + d’ 
= ((ab)'c)' + ((a'c)'d)' + ((bc)'d)' + (ad)'
= ab + c' + a'c + d' + bc + d' + a' + d'
= ab + c' + a'c + bc + a' + d'
= ab + c' + bc + a' + d'
= b + c' + bc + a' + d'
= a' + b + c' + d'
Question 95 
0110  
1011  
1101  
1111 
Question 96 
(135103.412)_{O}  
(564411.412)_{O}  
(564411.205)_{O}  
(135103.205)_{O} 
= 1100000000010010.00100101  0000010111001110.10100000
= 1011101001000011.10000101
= 1011101000011.100001010
= (135103.412)_{O}
Question 97 
(The line T in the following figure is permanently connected to the ground)
0000  
0111  
1111  
None of these 
Since the problem is in the link T which is connected as input to NOR gate. So to check link T we have to make the output dependent on T by deactivating link M. So to deactivate link M, the output at M should be 0, as link M is input to NOR gate. So, to output at M as 0,
X1 = 1
X2 = 1
X3 = 1
X4 = 0
∴ None of the given option is correct.
Question 98 
Hence, option (A) matches.
Consider the following expression
ad' + (ac)' + bc'd
Which of the following expressions does not correspond to the Karnaugh Map obtained for the above expression??
Question 99 Explanation: Let's check for option (C): a'c' + ad' + abc' + c'd Not equivalent to the Kmap, we get in previous question.
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flipflops) will delay the phase of f by 180°? Question 100 Explanation: Duty cycle is the period of time where the signal high, i.e. 1. 50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0. The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock. Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0. Like the below image. Now to find the answer we can choose elimination method. F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa. So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only. To have the above behaviour, the second D flipflop which produces the final output should be negative edge triggered. because whatever the 2nd flipflop produces, that is the output of the complete circuit. So, we can eliminate option a, d. Now either b or c can be answer. How the flipflop chain works in option b and c is as below. —> F changes at negative edge. —> But flipflop1 responds at next positive edge. —> After this flipflop2 responds at next negative edge. That means flipflop2 produces the same input which is given to flipflop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f. Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift. Option c) we are giving f, so that the output is f with 180 degrees phase shift. Hence option C is the answer.
We consider the addition of two 2’s complement numbers b_{n1}b_{n2}...b_{0} and a_{n1}a_{n2}…a_{0}. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_{n1}c_{n2}c_{0} and the carryout by c_{out}. Which one of the following options correctly identifies the overflow condition?
Question 101 Explanation: There is an overflow if 1. The sign bits are same i.e MSB bits are same. 2. Carry_in ≠ Carry_out. In option B, the MSB are equal.
Consider numbers represented in 4bit gray code. Let h_{3}h_{2}h_{1}h_{0} be the gray code representation of a number n and let g_{3}g_{2}g_{1}g_{0} be the gray code of (n+1) (modulo 16) value of the number. Which one of the following functions is correct?
Question 102 Explanation: g_{2}(h_{3}h_{2}h_{1}h_{0}) = Σ(2,4,5,6,7,12,13,15)
Consider a Boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i_{1} = 〈w_{1}, x_{1}, y_{1}, z_{1}〉 and i_{2} = 〈w_{2}, x_{2}, y_{2}, z_{2}〉, we would like the function to remain true as the input changes from vectors i_{1} to i_{2} (i_{1} and i_{2} differ in exactly one bit position), without becoming false momentarily. Let f(w, x, y, z) = ∑(5, 7, 11, 12, 13, 15). Which of the following cube covers of f will ensure that the required property is satisfied? Question 103 Explanation: Static hazard is the situation where, when one input variable changes, the output changes momentarily before stabilizing to the correct value. The most commonly used method to eliminate static hazards is to add redundant logic (consensus terms in the logic expression). f = X_{1} * X_{2} + X_{1}' * X_{3} If (X_{1},X_{2},X_{3}) = (1,1,1) then f=1 because X_{1} * X_{2} =1 X_{1}' * X_{3} = 0. Let the input is changed from 111 to 011 , then f = 1 because X_{1} * X_{2} = 0 X_{1}' * X_{3} =1. The output f will be momentarily 0 if AND gate X_{1} * X_{2} is faster than the AND gate X_{1}' * X_{}3. This Hazard can be avoided by adding the term X_{2} * X_{3} (because X_{1} is in true form in first term and in complement form in the second term . So pick the fixed terms X_{2} and X_{3} from both terms) to f i.e f = X_{1} * X_{2} + X_{1}' * X_{3} + X_{2} * X_{3} Option D is equivalent to f(w, x, y, z) = ∑(5,7,11,12,13,15)
Question 104 Explanation: f = yx + y’ (zy’+z’x) = xy + zy’ + y’z’x = x(y+y’z’) + zy’ = x(y+z’) + y’z = xy + xz’ + y’z
Given two three bit numbers a_{2}a_{1}a_{0} and b_{2}b_{1}b_{0} and c, the carry in, the function that represents the carry generate function when these two numbers are added is: Question 105 Explanation: Initial Carry c is not included in any option. Hence c=0. Carry c_{1} = a_{0}b_{0} Carry c_{2} = a_{2}b_{2} + c_{1}(a_{2} ⊕ b_{2} ) = a_{1}b_{1} +c_{1} (a_{1} b’_{1}+ a’_{1} b_{1} ) = a_{1}b_{1} +c_{1} a_{1} b’_{1}+ c_{1} a’_{1} b_{1} = (a_{1}b_{1} + c_{1}a_{1} b’_{1})+ (c_{1} a’_{1} b_{1} + a_{1}b_{1} ) = a_{1}(b_{1}+c_{1}) +b_{1} (c_{1} + a_{1}) = a_{1}b_{1}+b_{1}c_{1}+a_{1}c_{1} Carry c_{3} = a_{2}b_{2} + c_{2}(a_{2} ⊕ b_{2}) = a_{2}b_{2} + c_{2}(a’_{2}b_{2} + a_{2}b’_{2} ) = a_{2}b_{2} + b_{2}c_{2} + a_{2}c_{2} = a_{2}b_{2}+a_{2}a_{1}b_{1}+a_{2}a_{1}a_{0}b_{0}+a_{2}a_{0}b_{1}b_{0}+a_{1}b_{2}b_{1}+a_{1}a_{0}b_{2}b_{0}+a_{0}b_{2}b_{1}b_{0}
Consider the circuit in the diagram. The ⊕ operator represents ExOR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
Question 106 Explanation: D2 = q1,
D1= q0 ⊕ q2,
D0=external input
The addition of 4bit, two’s complement, binary numbers 1101 and 0100 results in
Question 107 Explanation: 2's complement of 1101 = 0011 2's complement of 1100 = 1100 Add = 1111 Now convert 1111 to normal form. ⇒ 0000 (1's complement) ⇒ 0001 (2's complement) No carry bit.
The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map.
Which of the product terms given below is an essential prime implicant of the function?
Question 108 Explanation: Essential prime implicants which are grouped only by only one method or way. So, in the given question cornor's ones are grouped by only one method.
The majority function is a Boolean function f(x, y, z) that takes the value 1 whenever a majority of the variables x, y, z and 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively,
Question 109 Explanation: Output of the function is x' P + x Q. Majority means at least two inputs should be 1. Whenever the majority of the variables have value 1, the output is 1. The following combinations produce output 1. 110, 101, 111, and 011 The circuit has 3 inputs namely x, y and z with x as the selection line to MUX. Consider Majority cases. Case 1: x=1 x y z 1 1 0 When x is 1 then at least one of y and z should be 1. Then P is OR gate. 1 0 1 1 1 1 Case 2: x=0 0 1 1 When x is 0 both y and z should be 1. So Q is AND gate
When multiplicand Y is multiplied by multiplier X = xn  1xn2 ....x0 using bitpair recoding in Booth's algorithm, partial products are generated according to the following table.
The partial products for rows 5 and 8 are
Question 110 Explanation: ⇒ 2Y and 0
Question 111 Explanation: f(X,Y,Z) = ((XY’)’ (YZ))’ = ((X’+Y) YZ)’ = (X’YZ + YZ)’ = ((X’+1) YZ)’ = (YZ)’
The range of integers that can be represented by an n bit 2's complement number system is:
Question 112 Explanation: The maximum (positive) n bit number is 011….1 (i.e., 0 followed by n1 ones) which is equal to 2^{n1}  1. The smallest (negative) n bit number is 100..0 (i.e., 1 followed by n1 zeros) which is equal to  2^{n1}. 1000...00 0111...11 < 1’s complement 1000..00 < 2’s complement =  2^{n1}
Consider the following floating point format
Mantissa is a pure fraction in signmagnitude form. The decimal number 0.239 × 2^{13} has the following hexadecimal representation (without normalization and rounding off :
Question 113 Explanation: Sign Bit = 0 Convert 0.239 to binary 0.239 * 2 = 0.478 0.478 * 2 = 0.956 0.956 * 2 = 1.912 0.912 * 2 = 1.824 0.824 * 2 = 1.648 0.648 * 2 = 1.296 0.296 * 2 = 0.512 0.512 * 2 = 1.024 Mantissa = (0. 00111101)_{2} Bias= 64. So biased exponent is 13+64 = 77= (1001101)_{2} 0.239 × 2^{13} = 0 1001101 00111101 = 0100 1101 0011 1101 = 4 D 3 D
Consider the following floating point format
Mantissa is a pure fraction in signmagnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0's are padded in while shifting a field. The normalized representation of the above number (0.239 × 2^{13}) is:
Question 114 Explanation: Sign Bit = 0 Convert 0.239 to binary 0.239 * 2 = 0.478 0.478 * 2 = 0.956 0.956 * 2 = 1.912 0.912 * 2 = 1.824 0.824 * 2 = 1.648 0.648 * 2 = 1.296 0.296 * 2 = 0.512 0.512 * 2 = 1.024 Mantissa = (0. 00111101)_{2} 0.239 × 2^{13} = 1.11101000 x 2^{10} < Normalized Mantissa Bias = 64. So biased exponent is 10+64 = 74 = (1001010)_{2} 0.239 × 2^{13} = 0 1001010 11101000 = 0100 1010 1110 1000 = (4 A E 8)_{16}
Consider the following circuit
The flipflops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:
Question 115 Explanation:
Consider the following circuit involving a positive edge triggered D FF.
Consider the following timing diagram. Let Ai represent the logic level on the line A in the ith clock period.
Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
Question 116 Explanation: Input will be accepted by the flipflop after the cycle gets finished, because +ve edge is occuring at the end of the clock cycle only.
The hexadecimal representation of 657_{8} is
Question 117 Explanation: (657)_{8} = (110 101 111)_{2} Make 3 zeros on the left side so that the number of bits is multiple of 4. = (0001 1010 1111)_{2} = (1 A F)_{16}
The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is:
Question 118 Explanation: f(A,B,C,D) = A'C'D + BC'D' + AB'D
A twoway switch has three terminals a, b and c. In ON position (logic value 1), a is connected to b, and in OFF position, a is connected to c. Two of these twoway switches S1 and S2 are connected to a bulb as shown below. Which of the following expressions, if true, will always result in the lighting of the bulb ? Question 119 Explanation: The bulb will be on when both the switch S1 and S2 are in same state, either OFF (or) ON: From this we can clearly know that given is EXNOR operation i.e., (S1⊙S2) = (S1⊕S2)'
How many pulses are needed to change the contents of a 8bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
Question 120 Explanation: The 8 bit counter will be 0255 to move from 10101100 (172) to 1000111 (39). → First counter is move from 172 to 255 = 83 pulses → 255 to 0 = 1 pulse → 0 to 39 = 39 pulses Total = 83 + 1 + 39 = 123 pulses
A line L in a circuit is said to have a stuckat0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuckat1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuckat fault if one or more lines have stuck at faults. The total number of distinct multiple stuckat faults possible in a circuit with N lines is
Question 121 Explanation: Answer should be 3^{N}1. This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3^{N}. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuckatfaults possible in a circuit with N lines is 3^{N}  1.
(34.4)_{8} × (23.4)_{8} evaluates to
Question 122 Explanation: First convert (34.4)_{8} and (23.4)_{8} to decimal. (34.4)_{8} = 3×8^{1} + 4×8^{0} + 4×8^{1} = 24 + 4 + 0.5 = (28.5)_{10} (23.4)_{8} = 2×8^{1} + 3×8^{0} + 4×8^{1} = 16 + 3 + 0.5 = (19.5)_{10} Now, (28.5)_{10} × (19.5)_{01} = (555.75)_{10} Now, (555.75)_{10} = ( ? )_{8} To convert the integer part, We get, 1053. To convert the fractional part, keep multiplying by 8 till decimal part becomes 0, ∴ (555.75)_{10} = (1053.6)_{8}
The circuit shown below implements a 2input NOR gate using two 24 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
Question 123 Explanation: In MUX1, the equation is g = Ax + Bz' In MUX2, the equation is f = xg + yg' = x(Az+Bz') + y(Az+Bz')' Function f should be equal to (A+B)'. Just try to put the values of option (D), i.e., x=0, y=1, z=A, f = 0(AA+BA') +1(AA+BA')' = (A+B)' ∴ Option (D) is correct.
n instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?
Question 124 Explanation: In horizontal microprogramming we need 1 bit for every control word, therefore total bits in horizontal microprogramming = 20 + 70 + 2 + 10 + 23 = 125 Now lets consider vertical microprogramming. In vertical microprogramming no. of bits required to activate 1 signal in group of N signals, is ⌈log_{2} N⌉. And in the question 5 groups contains mutually exclusive signals, group 1 = ⌈log_{2} 20⌉ = 5 group 2 = ⌈log_{2} 70⌉ = 7 group 3 = ⌈log_{2} 2⌉ = 1 group 4 = ⌈log_{2} 10⌉ = 4 group 5 = ⌈log_{2} 23⌉ = 5 Total bits required in vertical microprogramming = 5 + 7 + 1 + 4 + 5 = 22 So, number of bits saved is = 125  22 = 103
The Boolean function x'y' + xy + x'y is equivalent to
Question 125 Explanation: x'y' + xy + x'y = x'y' + x'y + xy = x'(y'+y)+xy = x'⋅1+xy = x'+xy = (x'+x)(x'+y) = 1⋅(x'+y) = x'+y
In an SR latch made by crosscoupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Question 126 Explanation: The following circuit and truth table of a crosscouple SR latch with 2 NAND gates. Output of a NAND is 1 if at least one of its input is zero.
If 73_{x} (in basex number system) is equal to 54_{y} (in basey number system), the possible values of x and y are
Question 127 Explanation: (73)_{x} = (54)_{y} 7x+3 = 5y+4 7x5y = 1 Only option (D) satisfies above equation.
Question 128 Explanation: (113. + 111.) + 7.51 = (2) + 7.51 = 9.51 (✔️) 113. + (111. + 7.51) = 113. + (103.51) = 113. + 103 = 10 (✔️)
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?
Question 129 Explanation: = A + BD + BC = A + B (D + C) So minimum two OR gates and 1 AND gate is required. Hence, in total minimum 3 gates is required.
Question 130 Explanation: From given function 'f' we can draw, There are two EPI, A'C and AC'.
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2variable Boolean function f = T + R, without using any additional hardware?
Question 131 Explanation: Given, f = z'x + zy Put z=T, x=R, y=1 in f f = T'R + T = (T+T') (R+T) = T+R Hence, correct option is (A).
Question 132 Explanation: Sequence given is 0  2  3  1  0 or 00  10  11  01  00 From the given sequence, we have state table as, Now we have present state and next state, so we should use excitation table of T flipflop, From state table,
A 4bit carry lookahead adder, which adds two 4bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using twolevel ANDOR logic.
Question 133 Explanation: The 4bit addition will be calculated in 3 stages: 1) (2 time units) In 2 time units we can compute G_{i} and P_{i} in parallel, 2 time units for P_{i} since its an XOR operation and 1 time unit for G_{i} sinceits an AND operation. 2) (2 time units) Once G_{i} and P_{i} are available, we can calculate the carries, C_{i}, in 2 time units. Level1 we can compute all the conjunctions (AND). Example P_{3}G_{2}, P_{3}P_{2}G_{1}, P_{3}P_{2}P_{1}G_{0} and P_{3}P_{2}P_{1}P_{0}C_{0} which are required for C_{4}. Level2 we get the carries by computing the disjunction (OR). 3) (2 time units) Finally, we compute the sum in 2 time units, as its a XOR operation. Hence, the total is 2+2+2=6 time units.
Let A = 1111 1010 and B = 0000 1010 be two 8bit 2's complement numbers. Their product in 2's complement is
Question 134 Explanation: A = 1111 1010 = 6_{10} [2's complement number] B = 0000 1010 = 10_{10} [2's complement number] A×B = 6×10 =  60_{10} ⇒ 60_{10} = 10111100_{2} = 11000011_{2} (1's complement) = 11000100_{2} (2's complement)
What is the minimum number of NAND gates required to implement a 2input EXCLUSIVEOR function without using any other logic gate?
Question 135 Explanation: To create 2input ExclusiveOR function we require 4 NAND gates.
What is the minimum size of ROM required to store the complete truth table of an 8bit × 8bit multiplier?
Question 136 Explanation: Input: 2 lines, 8 bits each Possible combination in ROM = (2^{8} × (2^{8}) [size of truth table] = 2^{16} = 64 KB = 64 K ×16 bits
Using a 4bit 2’s complement arithmetic, which of the following additions will result in an overflow? (i) 1100 + 1100 (ii) 0011 + 0111 (iii) 1111 + 0111
Question 137 Explanation: In 2's complement arithmetic, overflow happens only when 1) Sign bit of two input numbers is 0, and the result has sign bit 1. 2) Sign bit of two input numbers is 1, and the result has sign bit 0. So, only (2) causes overflow.
The number (123456)_{8} is equivalent to
Question 138 Explanation: (123456)_{8} = (001 010 011 100 101 110)_{2} = (00 1010 0111 0010 1110)_{2} = (A72E)_{16} Also, (001 010 011 100 101 110)_{2} = (00 10 10 01 11 00 10 11 10)_{2} = (22130232)_{4}
The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to
Question 139 Explanation: For given min term the Kmap is, ⇒ A'C + AC' + AB'
Consider a parity check code with three data bits and four parity check bits. Three of the code words are 0101011, 1001101 and 1110001. Which of the following are also code words? I. 0010111 II. 0110110 III. 1011010 IV. 0111010
Question 140 Explanation: Let x_{1}, x_{2}, x_{3} are data bits, and c_{1}, c_{2}, c_{3} and c_{4} are parity check bits. Given transmitted codewords are By inspection we can find the rule for generating each of the parity bits, Now from above we can see that (I) and (III) are only codewords.
Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011?
Question 141 Explanation: Given: Binary numbers = 11111011 MSB bit is '1' then all numbers are negative 1's complement = 00000100 2's complement = 00000100 + 00000001 = 00000101 = 5 (A) 11100111  (25)_{10} (B) 11100100  (28)_{10 (C) 11010111  (41)10 (D) 11011011  (37)10 Answer: Option A (25 is divisible by 5)}
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
Question 142 Explanation: Each bit in Multiplier is ANDed with a bit in Multiplicand which produce n nbit numbers. The multiplication takes n units of time. The n nbit numbers are added by using (n1) nbit adders. The time taken by (n1) nbit adders is k*(n1) units. The total time is n+knk = Θ(n)
The following is a scheme for floating point number representation using 16 bits.
Bit position 15 14 . . . 9 8 . . . . .0 s e m Sign Exponent MantissaLet s,e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is: What is the maximum difference between two successive real numbers representable in this system?
Question 143 Explanation: Largest gap will be in between two most largest numbers. The largest number is 1.111111111× 2^{6231} = (2−2^{−9})×2^{31} Second largest number is 1.111111110×2^{6231} = (2−2^{8})×2^{31} Difference = (2−2^{−9})×2^{31}  (2−2^{8})×2^{31} = (2^{8}−2^{−9}) ×2^{31} = 2^{−9}×2^{31} = 2^{22}
A 1input, 2output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.
zk  nk = 2. In this case, the output at the kth and all subsequent clock ticks is 10. nk  zk = 2. In this case, the output at the kth and all subsequent clock ticks is 01.What is the minimum number of states required in the state transition graph of the above circuit?
Question 144 Explanation: Let q is the initial state. q_{0} ← Number of zeros is one more than number of ones. q_{1} ← Number of ones is one more than number of zeros. q_{00} ← Number of zeros is two more than number of ones. q_{11} ← Number of ones is two more than number of zeros.
The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the productofsum and sumofproduct representations respectively of the function given by the following Karnaugh map ? Here, X denotes "don't care"
Question 145 Explanation: For SOP, ⇒ w'y' + z'wx' + xyz' Total 8 literals are there. For POS, ⇒ (z' + w')(z' + y')(w' + x')(x + z + w) Total 9 literals are there.
Consider the ALU shown below If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and  denote addition and subtraction respectively) ?
Question 146 Explanation: The circuits performs 1) A+B when K=0 and C_{0} = 0. It is binary adder which performs addition of two binary numbers. 2) A  B = A+ B' + 1 when K=1 and C_{0} = 1 ; Here XOR gates produce B' if K=1. Since 1⊕b= b'. "1" in (A+B+1) is coming from C_{0}. Note: 2's complement of B is (B'+1). 3) A+1 when B=0, K=0, C_{0}= 1. Increments A.
Consider the following circuit composed of XOR gates and noninverting buffers.
The noninverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?
Question 147 Explanation: ⇒ a will always be equal to A.
Question 148 Explanation: ⇒ xz' + zx'
The decimal value 0.25
Question 149 Explanation: 1^{st} Multiplication iteration: Multiply 0.25 by 2. 0.25×2 = 0.50 (product) Fractional part = 0.50 Carry = 0 2^{nd} Multiplication iteration: Multiply 0.50 by 2. 0.50×2 = 1.00 (product) Fractional part = 0.00 Carry = 1 The fractional part in the 2^{nd} iteration becomes zero and so we stop the multiplication iteration. Carry from 1^{st} multiplication iteration becomes MSB and carry from 2^{nd} iteration becomes LSB. So the result is 0.01.
The 2’s complement representation of the decimal value 15 is
Question 150 Explanation: 15 = 1111 15 = 11111 1's complement = 10000 2's complement = 10001
Sign extension is a step in
Question 151 Explanation: Sign extension is a step in converting a signed integer from on size to another.
In 2’s complement addition, overflow
Question 152 Explanation: The left most bit of positive value is zero. And left most bit for negative value is one. The value of 0+1 becomes 1. Then overflow never occurs.
Question 153 Explanation: f(x,y,z) = (f_{1}', (x,y,z) ⋅ f_{2}'(x,y,z) + f_{3}'(x,y,z)) = (Σ(0,1,3,5) ⋅ Σ(6,7) + Σ(1,4,5)) [Σ(0,1,3,5) and Σ(6,7) ⇒ No common terms] = (Σ(1,4,5))
Question 154 Explanation: F = (A'A_{0}'10 + A'A_{0}'11 + A'A_{0}'12 + A_{1}A_{0}13) EN F = (xyz' + xyz + y'zy + zy')z' = (xyz' + xyz + y'z(y+1))z' = (xyz' + xyz + y'z)z' = (xy(z+z') + y'z)z' = (xy + y'z)z' = (xyz' + y'zz') = (xyz')
Let f(A,B) = A'+B. Simplified expression for function f (f (x + y, y), z) is
Question 155 Explanation: f(A,B) = A' +B ⇒ f(f((x+y), y), z) ⇒ f(((x+y)' + y), z) ⇒ f(((x'⋅y') + y), z) ⇒ f((x'⋅y') + y), z) ⇒ ((x'⋅y') + y)' + z ⇒ (x'⋅y')⋅y' + z ⇒ (x+y)⋅y' + z ⇒ (xy'+yy') + z ⇒ xy' + z
Question 156 Explanation:
The number 43 in 2’s complement representation is
Question 159 Explanation: Positive integers are represented in its normal binary form while negative numbers are represented in its 2′s complement form. Binary representation of 43 is 00101011.
Question 160 Explanation: Just put the values of each options in the equation and check it.
Question 161 Explanation: The Kmap represents the following expression
Minimal POS: w(x+y)
minimal SOP: wx+wy
SOP(not minimal): (w+x) (w’+y) (x’ +y)
Question 162 Explanation: Here clocks are applied to both flip flops simultaneously. When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1. Input to D flip flop will be 0(initial value of P) so op at Q will be 0
Question 163 Explanation: Given: 32 bits representation. So, the maximum precision can be 32 bits (In 32bit IEEE representation, maximum precision is 24 bits but we take best case here). This means approximately 10 digits. A = 2.0 * 10^{30}, C = 1.0 So, A + C should make the 31^{st} digit to 1, which is surely outside the precision level of A (it is 31^{st} digit and not 31^{st} bit). So, this addition will just return the value of A which will be assigned to Y. So, Y + B will return 0.0 while X + C will return 1.0.
Question 165 Explanation:
Booth’s coding in 8 bits for the decimal number –57 is
Question 167 Explanation: Represent the multiplier in 2's complement form. 57 = 1100 0111 In Booth's algorithm, an operation (ADD or SUB) or/and Arithmetic Right Shift (ARS) operation is performed based on two least significant bits(Q0 Q1) of Multiplier. (Note: After RIGHT shift operation bits in higher significant positions move to lower significant position)
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
Question 168 Explanation: Total no. of gates being used for 'n' bit multiplication in an array multiplier (n*n) = (2n1) Total delay = 1 * 2n  1 = O(2n  1) = n
The number of full and halfadders required to add 16bit numbers is
Question 169 Explanation: For Least Significant Bit we do not need a full adder since initially carry is not present. But for rest of bits we need full address since carry from previous addition has to be included into the addition operation. So, in total 1 half adder and 15 full adders are required.
Zero has two representations in
Question 170 Explanation: Sign magnitude: +0 = 0000 0 = 1000 1's complement: +0 = 0000 0 = 1111
Question 171 Explanation: B⊕(B⊕(B⊕...) n times Consider: B⊕(B⊕B) = B⊕0 = 0 (if consider n times it remains unchanged)
A multiplexor with a 4 bit data select input is a
Question 172 Explanation: For 'n' bit data it selects 2^{n} : 1 input For 4 bit data it selects 2^{4} : 1 = 16: 1 input
The threshold level for logic 1 in the TTL family is
Question 173 Explanation: Voltage is to be below V_{cc} = 5V but above 2.8V
The octal representation of an integer is (342)_{8}. If this were to be treated as an eightbit integer is an 8085 based computer, its decimal equivalent is
Question 174 Explanation: (342)_{8} = (011 100 010)_{2} = (1110 0010)_{2} If this can be treated as 8 bit integer, then the first becomes sign bit i.e., '1' then the number is negative. 8085 uses 2's complement then ⇒ 30
Question 175 Explanation:
Which of the following operations is commutative but not associative?
Question 176 Explanation: NAND operation is commutative but not associative.
Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if it is stored as an integer rather than in character form?
Question 177 Explanation: We assume byte addressable memory  nothing smaller than a byte can be used. We have four digits. So to represent signed 4 digit numbers we need 5 bytes, 4 bytes for four digits and 1 for the sign. So required memory = 5 bytes. Now, if we use integer, the largest no. needed to represent is 9999 and this requires 2 bytes of memory for signed representation. 9999 in binary requires 14 bits. So, 2 bits remaining and 1 we can use for sign bit. So, memory savings, = 5  2/5 × 100 = 60%
Question 180 Explanation: In sum of terms,any term is an implicant because it implies the function. So xz is an implicant and hence 'C' is the answer.
Question 182 Explanation: f = f_{1}⋅f_{2} + f_{3} Since, f_{1} and f_{2} are in canonical sum of products form, f_{1}⋅f_{2} will only contain their common terms that is f_{1}⋅f_{2} = Σ8. Now, Σ8 + f_{3} = Σ8,9 So, f_{3}= Σ9
A ROM is sued to store the table for multiplication of two 8bit unsigned integers.
The size of ROM required is
Question 183 Explanation: When we multiply the two 8 bit numbers result will reach upto 16 bits. So we require 16 bits for each multiplication output. No. of results possibe = 2^{8} × 2^{8} = 2^{16} = 64K Then total size of ROM = 64K × 16
Both’s algorithm for integer multiplication gives worst performance when the
multiplier pattern is
Question 184 Explanation: When the pairs 01 (or) 10 occur frequently in the multiplier. In that case Booth multiplication gives worst performance.
Question 185 Explanation: Maximum value of mantissa will be 23, is where a decimal point is assumed before first 1. So the value is 1  2^{23}.
Consider the circuit in the figure below which has a 4 bit binary number b_{3}b_{2}b_{1}b_{0} as input and a five bit binary number d_{4}d_{3}d_{2}d_{1}d_{0} as output.
Question 186 Explanation: Here ф means 0. Whenever, b_{2} = b_{3} = 1, then only 0100, i.e., 4 is added to the given binary number. Lets write all possibilities for b. Note that the last 4 combinations leads to b_{3} and b_{2} as 1. So, in these combinations only 0010 will be added. 1100 is 12 1101 is 13 1110 is 14 1111 is 15 in binary unsigned number system. 1100 + 0100 = 10000 1101 + 0100 = 10001, and so on. This is conversion to radix 12.
Question 188 Explanation: Correct option is
Question 189 Explanation: For verification, just put up the values and check for AND, OR operations and their outputs.
The number of flipflops required to construct a binary modulo N counter is __________
Question 192 Explanation: For modN counter we need ⌈log_{2} N⌉ flip flops.
Consider nbit (including sign bit) 2’s complement representation of integer number. The range of integer values, N, that can be represented is _________ ≤ N ≤ _________
Question 194 Explanation: So finally, we can write
Question 195 Explanation: Circuit behaves as shift register and mod6 counter. Note that this is the Johnson counter which is the application of shift register. And Johnson counter is mod2N counter.
Question 196 Explanation: (a) 1*2^{2} + 1*2^{1} + 0*2^{0} + 1*2^{1} + 0*2^{2} + 1*2^{3} = 4 + 2 + 0 + 0.5 + 0 + 0.125 = 6.625 (b) 1118 mod 16 = E, quotient = 69 69 mod 16 = 5, quotient = 4 4 mod 16 = 4 Writing the mods result in reverse order gives (45E)_{H}.
A ROM is used to store the Truth table for a binary multiple unit that will multiply two 4bit numbers. The size of the ROM (number of words × number of bits) that is required to accommodate the Truth table is M words × N bits. Write the values of M and N.
Question 197 Explanation: Input will consist of 8 bit (two 4bit numbers) = 2^{8} address. Output will be of 8 bits. So memory will be of 2^{8} × 8. So, M = 256, N = 8.
Question 198 Explanation: We can write this as ⇒ ABC + B'C' + A'C'
Consider a 3bit error detection and 1bit error correction hamming code for 4bit date. The extra parity bits required would be ________ and the 3bit error detection is possible because the code has a minimum distance of ________
The operation which is commutative but not associative is:
Question 200 Explanation: NAND and NOR operation follow commutativity but do not follow associativity.
All digital circuits can be realized using only
Question 201 Explanation: NOR gate, NAND gate, Multiplexers and Half adders can also be used to realize all digital circuits.
Question 202 Explanation: ⇒ y'z + xy
Question 203 Explanation: Given clock is +edge triggered. See the first positive edge. X is 0, and hence the output is 0, because Y = Q_{1N} = D_{1}×Q_{0}' = 0⋅Q_{0}' = 0 At second +edge, X is 1 and Q_{0}' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns). At third +ve edge, X is 1 and Q_{0}' is 0, so output is 0. Now output never changes back to 1 as Q_{0}' is always 0 and when Q_{0}' finally becomes 1, X is 0. Hence option (A) is the correct answer.
The 2’s complement representation of (539)_{10} in hexadecimal is
Question 204 Explanation: (539)_{10} = (0010 0001 1011)_{2} For (539)_{10} = (1101 1110 0100)_{2} 1's complement = (1101 1110 0100)_{2} 2's complement = (1101 1110 0101)_{2} = (DE5)_{16}
Question 205 Explanation: g = (a and x1′) or (b and x1) g = (1 and x1’) or (0 and x1) g = x1’ f = ac’ + bc f = (a and x2′) or (b and x2) f = (g and x2′) or (x1 and x2) f = x1’x2’ + x1x2
Question 206 Explanation:
Question 207 Explanation: (a)
The function is self dual because → There is no mutually exclusive pair. → No. of minterms = No. of maxterms (b) Write Minimal POS.
Question 208 Explanation:
Question 210 Explanation: Hexadecimal representation of a given no. is, (9753)_{16} It's binary representation is, 1001011101010011 ∴ The no. of 1's is 9.
When two 4bit binary number A = a_{3}a_{2}a_{1}a_{0} and B = b_{3}b_{2}b_{1}b_{0} are multiplied, the digit c_{1} of the product C is given by _________
Question 211 Explanation: ⇒ c_{1} = b_{1}a_{0} ⊕ a_{1}b_{0}
Question 212 Explanation: In synchronization, there is a less chance of hazards but it can increase the delay. Then the advantage is ease of avoiding problems due to hazards.
Question 213 Explanation: There should be bubbled connection between two gates Y = ((ABC)' + (DE)')' Y = ABC . DE Note: Open gate works as NOR gate.
Question 214 Explanation: 1) RAM is not a combinational circuit. For RAM, the input is the memory location selector and operation (read or write) and another byte (which can be input for write operation or output for read operation), and the output is either a success indicator (for write operation) or the byte at the selected location (for read operation). It does depend on past inputs, or rather, on the past write operations at the selected byte. This is a sequential logic circuit. 2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
The total number of Boolean functions which can be realised with four variables is:
Question 215 Explanation: Total no. of Boolean functions which can be realized with four variables is:
Question 216 Explanation: Let us suppose initially output of all JK flip flop is 1. So we can draw below table to get the output Q_{3}. From the above table Q_{3} that is output is 1111 0001 0011 010. So, answer is (C).
The exponent of a floatingpoint number is represented in excessN code so that:
Question 218 Explanation: To avoid extra work, excessN code is used so that all exponent can be represented in positive numbers, starting with 0.
The refreshing rate of dynamic RAMs is in the range of
Question 219 Explanation: During a 2 millisecond interval all dynamic RAM memory is refreshed.
There are 219 questions to complete.
