Carry Lookahead Adder

Question 1
6, 3
10, 4
6, 4
10, 5
       Digital Logic Design        Carry Lookahead Adder       Gate-2007
Question 1 Explanation: 
Formula: n(n+1)/2 AND gates and n OR gates are needed for an n-bit carry look ahead circuit for addition of two binary numbers.
Question 2

A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

4 time units
6 time units
10 time units
12 time units
       Digital Logic Design        Carry Lookahead Adder       Gate-2004
Question 2 Explanation: 
The 4-bit addition will be calculated in 3 stages:
1) (2 time units) In 2 time units we can compute Gi and Pi in parallel, 2 time units for Pi since its an XOR operation and 1 time unit for Gi sinceits an AND operation.
2) (2 time units) Once Gi and Pi are available, we can calculate the carries, Ci, in 2 time units.
Level-1 we can compute all the conjunctions (AND). Example P3G2, P3P2G1, P3P2P1G0 and P3P2P1P0C0 which are required for C4.
Level-2 we get the carries by computing the disjunction (OR).
3) (2 time units) Finally, we compute the sum in 2 time units, as its a XOR operation.
Hence, the total is 2+2+2=6 time units.
There are 2 questions to complete.