## Logic-Gates

 Question 1
Consider the Boolean function z(a,b,c).

Which one of the following minterm lists represents the circuit given above?
 A Z=Σ(0,1,3,7) B Z=Σ(2,4,5,6,7) C Z=Σ(1,4,5,6,7) D Z=Σ(2,3,5)
Digital-Logic-Design       Logic-Gates       GATE 2020
Question 1 Explanation:
The output of the given circuit is a+b’c.
Convert a+b’c into canonical form which is sum of minterms.
a+b’c = a(b+b’)(c+c’)+ (a+a’)b’c
= abc + abc’ + ab’c + ab’c’ + ab’c + a’b’c
=Σ(7,6,5,4,1)
 Question 2
Let and denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?
 A B C D
Digital-Logic-Design       Logic-Gates       Gate 2018
Question 2 Explanation:
 Question 3
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?
 A B C D
Digital-Logic-Design       Logic-Gates       Gate 2011
Question 3 Explanation:
All options except option ‘D’ gives EX-NOR gates
 Question 4
What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?
 A B C D
Digital-Logic-Design       Logic-Gates       2010
Question 4 Explanation:
f = ((P’Q’ + Q’R’)’ + ( P’R’ + Q’R’)’ )’
= (P’Q’ + Q’R’)( P’R’ + Q’R’)
= (P’Q’P’R’ + P’Q’Q’R’ + Q’R’P’R’ + Q’R’Q’R’)
= (P’Q’R’ + P’Q’R’ + P’Q’R’ + Q’R’)
= (P’Q’R’ + Q’R’)
= (Q’R’)
= (Q+R)’
 Question 5
What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates?
 A 2 B 3 C 4 D 5
Digital-Logic-Design       Logic-Gates       2009
Question 5 Explanation:
NOR is Complement of OR
AB+C
= (A+C)(B+C) ← Distribution of + over
= ((A+C)’+(B+C)’)’
1st NOR- (A+C)’. Let X = (A+C)’
2nd NOR- (B+C)’. Let Y = (B+C)’
3rd NOR- (X+Y)’
 Question 6
What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?
 A 3 B 4 C 5 D 6
Digital-Logic-Design       Logic-Gates       Gate 2004-IT
Question 6 Explanation:

To create 2-input Exclusive-OR function we require 4 NAND gates.
 Question 7
Consider the following circuit composed of XOR gates and non-inverting buffers. The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?
 A 1 B 2 C 3 D 4
Digital-Logic-Design       Logic-Gates       Gate-2003
Question 7 Explanation:

⇒ a will always be equal to A.
 Question 8

 A x NAND X B x NOR x C x NAND 1 D x NOR 1
Digital-Logic-Design       Logic-Gates       Gate-1999
Question 8 Explanation:
 Question 9

 A A = 0, B = 0, C = 1 B A = 0, B = 1, C = 1 C A = 1, B = 0, C = 1 D A = 1, B = 1, C = 1
Database-Management-System       Logic-Gates       Gate-1999
Question 9 Explanation:

So the above equation is satisfied if either C=0 or A=0 and B=1.
Hence, Option (B) is correct.
 Question 10
Which of the following operations is commutative but not associative?
 A AND B OR C NAND D EXOR
Digital-Logic-Design       Logic-Gates       Gate-1998
Question 10 Explanation:
NAND operation is commutative but not associative.
 Question 11

 A B C D E None of the above.
Digital-Logic-Design       Logic-Gates       Gate-1994
Question 11 Explanation:
 Question 12

 A exclusive OR B exclusive NOR C NAND D NOR E None of the above
Digital-Logic-Design       Logic-Gates       Gate-1993
Question 12 Explanation:

So finally, we can write
There are 12 questions to complete.
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