Machine-Instructions

Question 1

A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4.Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ________.

A
32
B
33
C
34
D
35
       Computer-Organization       Machine-Instructions       Gate 2018
Question 1 Explanation: 
Instruction size = 2−byte.
So, total number of instruction encodings = 216
There are 16 possible integer registers, so no. of bits required for an integer operand = 4
There are 64 possible floating point registers, so no. of bits required for a floating point operand = 6
Type-1 instructions:
There are 4 type-1 instructions and each takes 3 integer operands.
No. of encodings consumed by type-1 = 4 × 24 × 24 × 24 =214.
Type-2 instructions:
There are 8 type-2 instructions and each takes 2 floating point operands.
No. of encodings consumed by Type-2 instructions = 8 × 26 x 26 = 215.
Type-3 instructions:
There are 14 type-3 instructions and each takes one integer operand and one floating point operand.
No. of encodings consumed by Type-3 instructions = 14 × 24 x 26 = 14336.
So, no. of encodings left for Type-4 = 216 − (214 + 215 + 14336) = 2048.
Since type-4 instructions take one floating point register, no. of different instructions of Type-4 = 2048 / 64 = 32.
Question 2

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________.

A
16 bits
B
17 bits
C
18 bits
D
19 bits
       Computer-Organization       Machine-Instructions       GATE 2016 set-2
Question 2 Explanation: 
6 bits are needed for 40 distinct instructions (because, 25 < 40 < 26)
5 bits are needed for 24 general purpose registers (because, 24 < 24 < 25)
32-bit instruction word has an opcode (6 bit), two register operands (total 10 bits) and an immediate operand (x bits).
The number of bits available for the immediate operand field
⇒ x = 32 – (6 + 10) = 16 bits
Question 3

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register r identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.

A
500 bytes
B
501 bytes
C
502 bytes
D
503 bytes
       Computer-Organization       Machine-Instructions       GATE 2016 set-2
Question 3 Explanation: 
One instruction is divided into five parts,
(i) The opcode- As we have instruction set of size 12, an instruction opcode can be identified by 4 bits, as 24 = 16 and we cannot go any less.
(ii) & (iii) Two source register identifiers- As there are total 64 registers, they can be identified by 6 bits. As they are two i.e. 6 bit + 6 bit.
iv) One destination register identifier- Again it will be 6 bits.
v) A twelve bit immediate value- 12 bit.
Adding them all we get,
4 + 6 + 6 + 6 + 12 = 34 bit = 34/8 byte = 4.25 bytes.
Due to byte alignment total bytes per instruction = 5 bytes.
As there are 100 instructions, total size = 5*100 = 500 Bytes.
Question 4
 

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

    (S1) A memory operand
    (S2) A processor register
    (S3) An implied accumulator register
A
Either S1 or S2
B
Either S2 or S3
C
Only S2 and S3
D
All of S1, S2 and S3
       Computer-Organization       Machine-Instructions       GATE 2015 (Set-01)
Question 4 Explanation: 
Any implied register is never explicitly mentioned as an operand in an operation.
So as the question asks what can be specified using the address fields, implied accumulator register can't be represented in address field.
So, S3 is wrong.
Hence Option A is the correct answer.
Question 5
 
A
(016A)16
B
(016C)16
C
(0170)16
D
(0172)16
       Computer-Organization       Machine-Instructions       GATE 2015 -(Set-2)
Question 5 Explanation: 
Here the memory is byte-addressable.
The CALL instruction is implemented as follows:
-Store the current value of PC in the stack
pc is 2 bytes so when we store pc in stack SP is increased by 2 so current value of SP is (016E)16+2 -Store the value of PSW register in the stack
psw is 2 bytes, so when we store psw in stack SP is increased by 2
so current value of SP is (016E)16+2+2=(0172)16
Question 6
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long.  It needs to support 45 instructions, which have an immediate operand in addition to two register operands.  Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.
A
16383
B
16384
C
16385
D
16386
       Computer-Organization       Machine-Instructions       GATE 2014(Set-01)
Question 6 Explanation: 
1 Word = 32 bits
Each instruction has 32 bits.
To support 45 instructions, opcode must contain 6-bits.
Register operand1 requires 6 bits, since the total registers are 64.
Register operand 2 also requires 6 bits

14-bits are left over for immediate Operand Using 14-bits, we can give maximum 16383, Since 214 = 16384 (from 0 to 16383)
Question 7
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory?
A
Immediate Addressing
B
Register Addressing
C
Register Indirect Scaled Addressing
D
Base Indexed Addressing
       Computer-Organization       Machine-Instructions       Gate 2011
Question 7 Explanation: 
Here 20 will act as base and content of R2 will be index.
Question 8
A
I only
B
II only
C
I and II only
D
I, II and III only
       Computer-Organization       Machine-Instructions       Gate-2008
Question 8 Explanation: 
RFE is a privileged instruction that is performed explicitly by the Operating System to switch from kernel mode to user mode at the end of handling an exception. Hence it has to be a trap. We know when a trap/interrupt is in execution, till its completion all other trap/interrupts will not be allowed to execute. So option D is correct answer.
Question 9

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

A
ADD (X)−, (X)
B
ADD (X), (X)−
C
ADD −(X), (X)+
D
ADD −(X), (X)+
       Computer-Organization       Machine-Instructions       Gate 2008-IT
Question 9 Explanation: 
Answer is A as 998 ← 1000 + 998(These are the memory locations).
Lets say SP is 1000 initially then after it calculates the EA of source (which is 1000 as it decrements after the EA). The destination becomes 998 and this is where we want to store the result as stack is decrementing.
In case of C and D it becomes,
998 ← 998 + 998
Question 10
   
A
2
B
3
C
5
D
6
       Computer-Organization       Machine-Instructions       Gate-2007
Question 10 Explanation: 
We can write the given four instructions using OP and MOV operations as below.
MOV a, R1
ADD b, R1
MOV c, R2
ADD d, R2
SUB e, R2
SUB R1, R2
MOV R2, m
So, from the above total no. of MOV instructions = 3
Question 11
A
10
B
11
C
20
D
21
       Computer-Organization       Machine-Instructions       Gate-2007
Question 11 Explanation: 
Firstly before the loop one memory reference is,
R1 ← m[3000]
Now loop will run 10 times because R1 contain value 10, and in each iteration of the loop there are two memory reference,
R2 ← M[R3]
M[R3] ← R2
So, in total, the no. of memory references are,
2(10) + 1 = 21
Question 12
A
100
B
101
C
102
D
110
       Computer-Organization       Machine-Instructions       Gate-2007
Question 12 Explanation: 
Loop will execute 10 times since the value in R1 stored is 10 in first step.
Now since the value will change at memory locations from 2000 to 2009 and will not affect the memory locations 2010.
Hence, the value at memory location 2010 it will be old value, i.e., 100.
Question 13

A
1005
B
1020
C
1024
D
1040
       Computer-Organization       Machine-Instructions       Gate-2007
Question 13 Explanation: 
Memory is byte addressable, so it requires 1 word or 4 bytes to perform a each operation such that
→ Starts at memory location 1000.

Interrupt occurs during the execution of information “INC R3”.
Then the value of address i.e., 1024 is pushed into the stack.
Question 14
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
A
400
B
500
C
600
D
700
       Computer-Organization       Machine-Instructions       Gate-2006
Question 14 Explanation: 
The instruction is of 24 bits or 3 bytes. Now the program starts at address 300 and the next will be 303 then, 306, then 309 and so on.
So finally we can say that the values in the program counter will always be the multiple of 3.
Hence, option (C) is correct.
Question 15

A
mask ← 0×1 □ pos
B
mask ← 0×ffffffff □ pos
C
mask ← pos
D
mask ← 0×f
       Computer-Organization       Machine-Instructions       Gate-2006
Question 15 Explanation: 
Using the following operation "temp→reg & mask" we are checking whether bit at position pos in register reg is 1 or not. For that mask should have 1 only in position pos. In all the other positions mask have 0s.
So for mask to have 1 only in position pos and 0s in all the other positions, we can get it by doing left shift on 1, pos number of times.
Out of the given options, in option A this left shift operation on 1 is performed pos number of times. Hence option A is the answer.
Question 16

A
2
B
3
C
4
D
5
       Computer-Organization       Machine-Instructions       Gate-2005
Question 16 Explanation: 
1 cycle → Increment
1 cycle → Load PC to MAR
1 cycle → Fetch memory and load to PC
----------------------------------------------
3 cycles
----------------------------------------------
Question 17
 
A
2
B
3
C
4
D
5
       Computer-Organization       Machine-Instructions       Gate-2005
Question 17 Explanation: 
Required minimum no. of clock cycles =3
i.e., for load, add and write.
1) Load Y
2) R1, add
3) output to R1
Question 18

A
3
B
4
C
5
D
6
       Computer-Organization       Machine-Instructions       Gate-2005
Question 18 Explanation: 
Total 4 memory cycles are required.
1 → To get 1st operand from memory address (Read).
1 → To get 2nd operand Address (Read).
1 → To get 2nd operand from the address given by previous memory (Read).
1 → To store first operand (Write).
3R + 1W = 4
Question 19
     
A
1007
B
1020
C
1024
D
1028
       Computer-Organization       Machine-Instructions       Gate-2004
Question 19 Explanation: 
Byte addressableb with size = 32 bits (word size) = 4 bytes
→ Interrupt occurs after executing halt instruction
So, number of instructions = 2+1+1+2+1 = 7
→ Each instruction with 4 bytes, then total instruction size = 7 * 4 = 28
→ Memory start location = 1000
→ Instruction saved location = 1000 + 28 = 1028
1028 is the starting address of next instruction.
Question 20
 
A
29
B
24
C
23
D
20
       Computer-Organization       Machine-Instructions       Gate-2004
Question 20 Explanation: 
Question 21

A
the number of 0 bits in A0
B
the number of 1 bits in A0
C
A0
D
8
       Computer-Organization       Machine-Instructions       Gate-2003
Question 21 Explanation: 
B is to be increments when a is moved to carry.
The code is counting the number of 1 bits in A0
Question 22
   
A
RRC A, #1
B
NOP ; no operation
C
LRC A, #1 ; left rotate A through carry flag by one bit
D
ADD A, #1
       Computer-Organization       Machine-Instructions       Gate-2003
Question 22 Explanation: 
Initially, the 8 bits will be,
a7, a6, a5, a4, a3 , a2, a1, a0
Now right rotate it once,
C0, a7, a6, a5, a4, a3 , a2, a1, now a0 is the new carry.
Now again right rotate it,
a0C0, a7, a6, a5, a4, a3 , a2

So after 8 rotations,
a6, a5, a4, a3 , a2, a1, a0C0 and carry is a7
Now, one more rotation will restore the original value of A0.
Hence, answer is Option (A).
Question 23
   
A
2
B
3
C
4
D
5
       Computer-Organization       Machine-Instructions       Gate-2001
Question 23 Explanation: 
T1: SP → MAR, 2 cycles (as SP is 16 bits and data bus is 8 bits so needs 2 cycles to move data)
T2: 8 → MBR, 1 cycle
T3: M[MAR] ← MBR, 2 cycles (As it is a memory operation)
So, total 5 clock cycles.
There are 23 questions to complete.