MachineInstructions
Question 1 
A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2byte instruction format. There are four categories of instructions: Type1, Type2, Type3 and Type4.Type1 category consists of four instructions, each with 3 integer register operands (3Rs). Type2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type4 category consists of N instructions, each with a floating point register operand (1F).
The maximum value of N is ________.
32  
33  
34  
35 
So, total number of instruction encodings = 2^{16}
There are 16 possible integer registers, so no. of bits required for an integer operand = 4
There are 64 possible floating point registers, so no. of bits required for a floating point operand = 6
Type1 instructions:
There are 4 type1 instructions and each takes 3 integer operands.
No. of encodings consumed by type1 = 4 × 2^{4} × 2^{4} × 2^{4} =2^{14}.
Type2 instructions:
There are 8 type2 instructions and each takes 2 floating point operands.
No. of encodings consumed by Type2 instructions = 8 × 2^{6} x 2^{6} = 2^{15}.
Type3 instructions:
There are 14 type3 instructions and each takes one integer operand and one floating point operand.
No. of encodings consumed by Type3 instructions = 14 × 2^{4} x 2^{6} = 14336.
So, no. of encodings left for Type4 = 2^{16} − (2^{14} + 2^{15} + 14336) = 2048.
Since type4 instructions take one floating point register, no. of different instructions of Type4 = 2048 / 64 = 32.
Question 2 
A processor has 40 distinct instructions and 24 general purpose registers. A 32bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand ﬁeld is __________.
16 bits  
17 bits  
18 bits  
19 bits 
5 bits are needed for 24 general purpose registers (because, 2^{4} < 24 < 2^{5})
32bit instruction word has an opcode (6 bit), two register operands (total 10 bits) and an immediate operand (x bits).
The number of bits available for the immediate operand field
⇒ x = 32 – (6 + 10) = 16 bits
Question 3 
Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has ﬁve distinct ﬁelds, namely, opcode, two source register identiﬁers, one destination register r identiﬁer, and a twelvebit immediate value. Each instruction must be stored in memory in a bytealigned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.
500 bytes  
501 bytes  
502 bytes  
503 bytes 
(i) The opcode As we have instruction set of size 12, an instruction opcode can be identified by 4 bits, as 2^{4} = 16 and we cannot go any less.
(ii) & (iii) Two source register identifiers As there are total 64 registers, they can be identified by 6 bits. As they are two i.e. 6 bit + 6 bit.
iv) One destination register identifier Again it will be 6 bits.
v) A twelve bit immediate value 12 bit.
Adding them all we get,
4 + 6 + 6 + 6 + 12 = 34 bit = 34/8 byte = 4.25 bytes.
Due to byte alignment total bytes per instruction = 5 bytes.
As there are 100 instructions, total size = 5*100 = 500 Bytes.
Question 4 
For computers based on threeaddress instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register
Either S1 or S2
 
Either S2 or S3  
Only S2 and S3  
All of S1, S2 and S3

So as the question asks what can be specified using the address fields, implied accumulator register can't be represented in address field.
So, S3 is wrong.
Hence Option A is the correct answer.
Question 5 
(016A)_{16}  
(016C)_{16}  
(0170)_{16}  
(0172)_{16} 
The CALL instruction is implemented as follows:
Store the current value of PC in the stack
pc is 2 bytes so when we store pc in stack SP is increased by 2 so current value of SP is (016E)_{16}+2 Store the value of PSW register in the stack
psw is 2 bytes, so when we store psw in stack SP is increased by 2
so current value of SP is (016E)_{16}+2+2=(0172)_{16}
Question 6 
16383  
16384  
16385  
16386 
Each instruction has 32 bits.
To support 45 instructions, opcode must contain 6bits.
Register operand1 requires 6 bits, since the total registers are 64.
Register operand 2 also requires 6 bits
14bits are left over for immediate Operand Using 14bits, we can give maximum 16383, Since 2^{14} = 16384 (from 0 to 16383)
Question 7 
Immediate Addressing  
Register Addressing  
Register Indirect Scaled Addressing  
Base Indexed Addressing 
Question 8 
I only  
II only  
I and II only
 
I, II and III only

Question 9 
Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.
ADD (X)−, (X)  
ADD (X), (X)−  
ADD −(X), (X)+  
ADD −(X), (X)+ 
Lets say SP is 1000 initially then after it calculates the EA of source (which is 1000 as it decrements after the EA). The destination becomes 998 and this is where we want to store the result as stack is decrementing.
In case of C and D it becomes,
998 ← 998 + 998
Question 10 
2  
3  
5  
6 
MOV a, R_{1}
ADD b, R_{1}
MOV c, R_{2}
ADD d, R_{2}
SUB e, R_{2}
SUB R_{1}, R_{2}
MOV R_{2}, m
So, from the above total no. of MOV instructions = 3
Question 11 
10  
11  
20  
21 
R1 ← m[3000]
Now loop will run 10 times because R1 contain value 10, and in each iteration of the loop there are two memory reference,
R2 ← M[R3]
M[R3] ← R2
So, in total, the no. of memory references are,
2(10) + 1 = 21
Question 12 
100  
101  
102  
110 
Now since the value will change at memory locations from 2000 to 2009 and will not affect the memory locations 2010.
Hence, the value at memory location 2010 it will be old value, i.e., 100.
Question 13 
1005
 
1020
 
1024  
1040

→ Starts at memory location 1000.
Interrupt occurs during the execution of information “INC R3”.
Then the value of address i.e., 1024 is pushed into the stack.
Question 14 
400  
500  
600  
700 
So finally we can say that the values in the program counter will always be the multiple of 3.
Hence, option (C) is correct.
Question 15 
mask ← 0×1 □ pos  
mask ← 0×ffffffff □ pos  
mask ← pos
 
mask ← 0×f

So for mask to have 1 only in position pos and 0s in all the other positions, we can get it by doing left shift on 1, pos number of times.
Out of the given options, in option A this left shift operation on 1 is performed pos number of times. Hence option A is the answer.
Question 16 
Consider the following data path of a CPU.
The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation  the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR 79. The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
Rn < = PC + 1; PC < = M[PC];
The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:
2  
3  
4  
5 
1 cycle → Load PC to MAR
1 cycle → Fetch memory and load to PC

3 cycles

Question 17 
2  
3  
4  
5 
i.e., for load, add and write.
1) Load Y
2) R_{1}, add
3) output to R_{1}
Question 18 
ADD A[R0], @ BThe first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is
3  
4  
5  
6 
1 → To get 1^{st} operand from memory address (Read).
1 → To get 2^{nd} operand Address (Read).
1 → To get 2^{nd} operand from the address given by previous memory (Read).
1 → To store first operand (Write).
3R + 1W = 4
Question 19 
1007  
1020  
1024  
1028 
→ Interrupt occurs after executing halt instruction
So, number of instructions = 2+1+1+2+1 = 7
→ Each instruction with 4 bytes, then total instruction size = 7 * 4 = 28
→ Memory start location = 1000
→ Instruction saved location = 1000 + 28 = 1028
1028 is the starting address of next instruction.
Question 21 
MOV B, # 0  ;  B ← 0  
MOV C, # 8  ;  C ← 8  
Z :  CMP C, # 0  ;  compare C with 0 
JZX  ;  jump to X if zero flag is set  
SUB C, # 1  ;  C ← C  1  
RRC A, # 1  ;  right rotate A through carry by one bit. Thus:  
;  if the initial values of A and the carry flag are a_{7}...a_{0} and  
;  c_{0} respectively, their values after the execution of this  
;  instruction will be c_{0}a_{7}...a_{1} and a_{0} respectively.  
JC Y  ;  jump to Y if carry flag is set  
JMP Z  ;  jump to Z  
Y :  ADD B, # 1  ;  B ← B + 1 
JMP Z  ;  jump to Z  
X : 
the number of 0 bits in A_{0}
 
the number of 1 bits in A_{0}
 
A_{0}  
8 
The code is counting the number of 1 bits in A_{0}
Question 22 
MOV B, # 0  ;  B ← 0  
MOV C, # 8  ;  C ← 8  
Z :  CMP C, # 0  ;  compare C with 0 
JZX  ;  jump to X if zero flag is set  
SUB C, # 1  ;  C ← C  1  
RRC A, # 1  ;  right rotate A through carry by one bit. Thus:  
;  if the initial values of A and the carry flag are a_{7}...a_{0} and  
;  c_{0} respectively, their values after the execution of this  
;  instruction will be c_{0}a_{7}...a_{1} and a_{0} respectively.  
JC Y  ;  jump to Y if carry flag is set  
JMP Z  ;  jump to Z  
Y :  ADD B, # 1  ;  B ← B + 1 
JMP Z  ;  jump to Z  
X : 
RRC A, #1
 
NOP ; no operation
 
LRC A, #1 ; left rotate A through carry flag by one bit  
ADD A, #1

a_{7}, a_{6}, a_{5, a4, a3 , a2, a1, a0 Now right rotate it once, C0, a7, a6, a5, a4, a3 , a2, a1, now a0 is the new carry. Now again right rotate it, a0C0, a7, a6, a5, a4, a3 , a2 ⁞ So after 8 rotations, a6, a5, a4, a3 , a2, a1, a0C0 and carry is a7 Now, one more rotation will restore the original value of A0. Hence, answer is Option (A). }
Question 23 
2  
3  
4  
5 
T2: 8 → MBR, 1 cycle
T3: M[MAR] ← MBR, 2 cycles (As it is a memory operation)
So, total 5 clock cycles.