## Memory-Interfacing

Question 1 |

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M×4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^{14}. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.

59% | |

60% | |

61% | |

62% |

Question 1 Explanation:

Time taken to refresh one row = 50 ns

There are 2

It is given that total refresh period is 2ms. The refresh period contains the time to refresh all the rows and also the time to perform read/write operation.

So % time spent in refresh = (Time taken to refresh all rows / refresh period)*100

= (0.82 ms / 2ms)*100

= 41%

So the % of time for read/write operation = 100 - 41 = 59%

There are 2

^{14}rows, so time taken to refresh all the rows = 2^{14}* 50ns = 0.82 millisecondsIt is given that total refresh period is 2ms. The refresh period contains the time to refresh all the rows and also the time to perform read/write operation.

So % time spent in refresh = (Time taken to refresh all rows / refresh period)*100

= (0.82 ms / 2ms)*100

= 41%

So the % of time for read/write operation = 100 - 41 = 59%

Question 2 |

A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _________ bits.

32 | |

34 | |

31 | |

33 |

Question 2 Explanation:

Maximum Memory = 4GB = 2

Size of a word = 2 bytes

Therefore, Number of words = 2

So, we require 31 bits for the address bus of the processor.

^{32}bytesSize of a word = 2 bytes

Therefore, Number of words = 2

^{32}/ 2 = 2^{31}So, we require 31 bits for the address bus of the processor.

Question 3 |

A main memory unit with a capacity of 4 megabytes is built using 1M 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is

100 nanoseconds | |

100*2 ^{10} nanoseconds | |

100*2 ^{20} nanoseconds | |

3200*2 ^{20} nanoseconds |

Question 3 Explanation:

Each chip capacity = 1M x 1-bit

Required capacity = 4MB

Number of chips needed = 4M*8 bits / 1M x 1-bit = 32 (1M x 1-bit)/(1M x 1-bit) = 32

Irrespective of the number of chips, all chips can be refreshed in parallel.

And all the cells in a row are refreshed in parallel too. So, the total time for refresh will be number of rows times the refresh time of one row.

Here we have 1K rows in a chip and refresh time of single row is 100ns.

So total time required =1K×100

=100 ×2

Required capacity = 4MB

Number of chips needed = 4M*8 bits / 1M x 1-bit = 32 (1M x 1-bit)/(1M x 1-bit) = 32

Irrespective of the number of chips, all chips can be refreshed in parallel.

And all the cells in a row are refreshed in parallel too. So, the total time for refresh will be number of rows times the refresh time of one row.

Here we have 1K rows in a chip and refresh time of single row is 100ns.

So total time required =1K×100

=100 ×2

^{10}nanosecondsQuestion 4 |

How many 32K × 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

8 | |

32 | |

64 | |

128 |

Question 4 Explanation:

Each chip capacity = 32K×1- bit

Needed memory capacity = 256K-bytes = 256K*8 bits

Number of chips needed = 256K*8 / 32K×1= 64

Needed memory capacity = 256K-bytes = 256K*8 bits

Number of chips needed = 256K*8 / 32K×1= 64

There are 4 questions to complete.