Microprocessor

Question 1
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
A
B
HOLD is active
C
READY is active
D
None of the above
       Computer-Organization       Microprocessor       Gate-2002
Question 1 Explanation: 
INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt.
Question 2
In 8085 which of the following modifies the program counter?
A
Only PCHL instruction
B
Only ADD instructions
C
Only JMP and CALL instructions
D
All instructions
       Computer-Organization       Microprocessor       Gate-2002
Question 2 Explanation: 
PCHL Instruction: Which can copy the content from H& L to PC.
ADD Instruction: increments the program counter.
JMP & CALL: Change the values of PC.
Question 3
 
A
AC = 0 and CY =0
B
AC = 1 and CY =1
C
AC = 1 and CY =0
D
AC = 0 and CY =1
       Computer-Organization       Microprocessor       Gate-2002
Question 3 Explanation: 
MOV H, 5DH
⇒ H = 0101 1101
MOV L, 6BH
⇒ L = 0110 1011
MOV A, H
A = 0101 1101
ADD L ⇒ A+L =

Here, AC=1; CY=0
Question 4
To put the 8085 microprocessor in the wait state
A
lower the HOLD input
B
lower the READY input
C
raise the HOLD input
D
raise the READY input
       Computer-Organization       Microprocessor       Gate-2000
Question 4 Explanation: 
If ready pin is high the microprocessor will complete the operation and proceeds for the next operation. If ready pin is low the microprocessor will wait until it goes high.
Question 5
The 8085 microprocessor responds to the present of an interrupt
A
as soon as the TRAP pin becomes ‘high’
B
by checking the TRAP pin for ‘high’ status at the end of each instruction each
C
by checking the TRAP pin for ‘high’ status at the end of the execution of each instruction
D
by checking the TRAP pin for ‘high’ status at regular intervals
       Computer-Organization       Microprocessor       Gate-2000
Question 5 Explanation: 
TRAP is non maskable interrupt . TRAP is active high, level, edge triggered non maskable highest priority interrupt. When TRAP line is active microprocessor insert intervals restarts automatically at vector location of TRAP.
Question 6
The address space of 8086 CPU is
A
one Megabyte
B
256 Kilobytes
C
1 K Megabytes
D
64 Kilobytes
       Computer-Organization       Microprocessor       Gate-1998
Question 6 Explanation: 
Note: Out of syllabus.
Question 7
RST 7.5 interrupt in 8085 microprocessor executes service routing from interrupt vector location
A
0000H
B
0075H
C
003CH
D
0034H
       Computer-Organization       Microprocessor       Gate-1997
Question 7 Explanation: 
RST7.5 then location is = 7.5*8 = 60 (8085 is 8 bit processor)
→ 60 in hexa decimal is 003CH.
Question 8
 
A
7AH
B
80H
C
50H
D
22H
       Computer-Organization       Microprocessor       Gate-1997
Question 8 Explanation: 
Note: Out of syllabus.
Question 9
Number of machine cycles required for RET instruction in 8085 microprocessor is
A
1
B
2
C
3
D
5
       Computer-Organization       Microprocessor       Gate-1996
Question 9 Explanation: 
1 for instruction fetch.
2 for stack operation.
Total no. of cycles = 2+1 = 3
Question 10
A single instruction to clear the lower four bits of the accumulator in 8085 assebly language?
A
XRI OFH
B
ANI FOH
C
XRI FOH
D
ANI OFH
       Computer-Organization       Microprocessor       Gate-1995
Question 10 Explanation: 
Here, we use the AND as a accumulator with immediate. F leaves the high nibble whatever it is, 0 clears the lower nibble.
→ The XOR's don't reliably clear random bits and ANI OF clears the upper nibble, not the lower nibble.
Question 11
 
A
Variables
B
Identifiers
C
Actual parameters
D
Formal parameters
       Computer-Organization       Microprocessor       Gate-1995
Question 11 Explanation: 
Formal arguments (or) formal parameters is a special kind of variables used in subroutime to refer to one of pieces of data provided as input to the subroutine.
Question 12
   
A
True
B
False
       Computer-Organization       Microprocessor       Gate-1994
Question 12 Explanation: 
Note: Out of syllabus.
The major reason of multiplexing address and data bus is to reduce the number of pins for address and data and dedicate those pins for other several functions of micro-processor.
Question 13
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ______
A
clock frequency can't go below this value.
       Computer-Organization       Microprocessor       Gate-1992
Question 13 Explanation: 
Clock frequency becomes low memory time period of clock becomes high. When this time period increases beyond the time period in which the non-volatile memory contents must be refreshed, we loose those contents. So clock frequency can't go below this value.
Question 14
Many of the advanced microprocessors prefetch instructions and store it in an instruction buffer to speed up processing. This speed up is achieved because _________
A
prefetching the instructions to be executed can save considerable amount of waiting time.
       Computer-Organization       Microprocessor       Gate-1992
Question 14 Explanation: 
Because CPU is faster than memory. Fetching the instructions from memory would require considerable amount of time while CPU is much faster. So, prefetching the instructions to be executed can save considerable amount of waiting time.
Question 15
PCHL is an instruction in 8085 which transfers the contents of the register pair HL to PC. This is not a very commonly used instruction as it changes the flow of control in rather ‘unstructured’ fashion. This instruction can be useful in implementing.
A
if ……. then ….. else ….. construct
B
while …… construct
C
case …… construct
D
call …… construct
       Computer-Organization       Microprocessor       Gate-1992
Question 15 Explanation: 
Note: Out of syllabus.
Question 16
A low memory can be connected to 8085 by using
A
INTER
B
C
HOLD
D
READY
       Computer-Organization       Microprocessor       Gate-2001
Question 16 Explanation: 
Communication is only possible when READY signal is set. So a low memory can be connected to 8085 by using READY signal.
Question 17
Using the 8087 arithmetic coprocessor with the 8087 CPU requires that the 8087 CPU is operated ________.
A
Out of syllabus.
       Computer-Organization       Microprocessor       Gate-1991
Question 18
 
A
Out of syllabus.
       Computer-Organization       Microprocessor       Gate-1991
Question 19
A
executes an instruction supplied by an external device through the INTA signal
B
executes an instruction from memory location 20H
C
executes a NOP
D
none of the above
       Computer-Organization       Microprocessor       Gate-1991
Question 19 Explanation: 
Note: Out of syllabus.
Question 20
 
A
latch the output of an I/O instruction into an external latch
B
deactivate the chip-select signal from memory devices
C
latch the 8 bits of address lines AD7-AD0 into an external latch
D
find the interrupt enable status of the TRAP interrupt
E
None of the above
       Computer-Organization       Microprocessor       Gate-1991
Question 20 Explanation: 
Note: Out of syllabus.
There are 20 questions to complete.