## Multiplexer

 Question 1
 A B C D
Digital-Logic-Design       Multiplexer       2016 set-01
Question 1 Explanation:
Output of 1st MUX is
Now
 Question 2
 A B C D
Digital-Logic-Design       Multiplexer       GATE 2014(Set-01)
Question 2 Explanation:
F(P,Q,R)= P’Q’ (0) + P’Q (1) + PQ’ (R) + PQ(R’)
= P’Q + PQ’R + PQR’
= Q(P’ + P R’) + PQ’R
= Q(P’ + R’) + PQ’R
= P’Q + QR’ + PQ’R
 Question 3

 A B P⊕Q⊕R C P+Q+R D
Digital-Logic-Design       Multiplexer       2010
Question 3 Explanation:
f= P’Q’ R + P’Q R’ + PQ’ R’ + PQR
= (P’Q’ + PQ)R + (P’Q+PQ’)R’
= (P⊕Q)’ R + (P⊕Q)R’
= (P⊕Q⊕R)
 Question 4
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?
 A 2n line to 1 line B 2n+1 line to 1 line C 2n-1 line to 1 line D 2n-2 line to 1 line
Digital-Logic-Design       Multiplexer       Gate-2007
Question 4 Explanation:
Both true and complement forms of all variables are necessary to implement any function of n variables.
A 2n X 1 multiplexer can implement any function of n variables. As n variables are given to select lines, so that true and complement forms of all variables get generated inside the MUX.
As one inverter is available, we can generate complement of one variable outside of the Multiplexer. And remaining (n-1) variables are given to select lines. With this we have true and complement form of all n variables.
So, the answer is 2n-1 X 1 MUX.
 Question 5

 A X1 = b, X2 = 0, X3 = a B X1 = b, X2 = 1, X3 = b C X1 = a, X2 = b, X3 = 1 D X1 = a, X2 = 0, X3 = b
Digital-Logic-Design       Multiplexer       Gate 2007-IT
Question 5 Explanation:
F = (bX1' + aX1)X3 + X2X3'
If we put
X1 = b
X2 = 0
X3 = a
Then we get,
F = ab
 Question 6

 A B C D
Digital-Logic-Design       Multiplexer       Gate-2006
Question 6 Explanation:
f = yx + y’ (zy’+z’x)
= xy + zy’ + y’z’x
= x(y+y’z’) + zy’
= x(y+z’) + y’z
= xy + xz’ + y’z
 Question 7
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware?
 A R to X, 1 to Y, T to Z B T to X, R to Y, T to Z C T to X, R to Y, 0 to Z D R to X, 0 to Y, T to Z
Digital-Logic-Design       Multiplexer       Gate-2004
Question 7 Explanation:
Given,

f = z'x + zy
Put z=T, x=R, y=1 in f
f = T'R + T = (T+T') (R+T) = T+R
Hence, correct option is (A).
 Question 8
What is the minimum size of ROM required to store the complete truth table of an 8-bit × 8-bit multiplier?
 A 32 K × 16 bits B 64 K × 16 bits C 16 K × 32 bits D 64 K × 32 bits
Digital-Logic-Design       Multiplexer       Gate 2004-IT
Question 8 Explanation:
Input: 2 lines, 8 bits each
Possible combination in ROM = (28 × (28) [size of truth table]
= 216
= 64 KB
= 64 K ×16 bits
 Question 9
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
 A Θ (1) B Θ (log n) C Θ (n) D Θ (n2)
Digital-Logic-Design       Multiplexer       Gate-2003
Question 9 Explanation:
Each bit in Multiplier is ANDed with a bit in Multiplicand which produce n n-bit numbers. The multiplication takes n units of time. The n n-bit numbers are added by using (n-1) n-bit adders. The time taken by (n-1) n-bit adders is k*(n-1) units.
The total time is n+kn-k = Θ(n)
 Question 10

 A xyz' B xy+z C x+y D None of the above
Digital-Logic-Design       Multiplexer       Gate-2002
Question 10 Explanation:
F = (A'A0'10 + A'A0'11 + A'A0'12 + A1A013) EN
F = (xyz' + xyz + y'zy + zy')z'
= (xyz' + xyz + y'z(y+1))z'
= (xyz' + xyz + y'z)z'
= (xy(z+z') + y'z)z'
= (xy + y'z)z'
= (xyz' + y'zz')
= (xyz')
 Question 11
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
 A On2 B O(n) C O(log n) D O(1)
Digital-Logic-Design       Multiplexer       Gate-1999
Question 11 Explanation:
Total no. of gates being used for 'n' bit multiplication in an array multiplier (n*n) = (2n-1)
Total delay = 1 * 2n - 1 = O(2n - 1) = n
 Question 12
A multiplexor with a 4 bit data select input is a
 A 4:1 multiplexor B 2:1 multiplexor C 16:1 multiplexor D 8:1 multiplexor
Digital-Logic-Design       Multiplexer       Gate-1998
Question 12 Explanation:
For 'n' bit data it selects 2n : 1 input
For 4 bit data it selects 24 : 1 = 16: 1 input
 Question 13

 A B C D
Digital-Logic-Design       Multiplexer       Gate-1996
Question 13 Explanation:
 Question 14

 A B A⊕B⊕C C A⊕B D
Digital-Logic-Design       Multiplexer       GATE-1987
Question 14 Explanation:
There are 14 questions to complete.