Multiplexer
Question 1 
Question 1 Explanation:
Output of 1^{st} MUX is
Now
Now
Question 2 
Question 2 Explanation:
F(P,Q,R)= P’Q’ (0) + P’Q (1) + PQ’ (R) + PQ(R’)
= P’Q + PQ’R + PQR’
= Q(P’ + P R’) + PQ’R
= Q(P’ + R’) + PQ’R
= P’Q + QR’ + PQ’R
= P’Q + PQ’R + PQR’
= Q(P’ + P R’) + PQ’R
= Q(P’ + R’) + PQ’R
= P’Q + QR’ + PQ’R
Question 3 
P⊕Q⊕R
 
P+Q+R  
Question 3 Explanation:
f= P’Q’ R + P’Q R’ + PQ’ R’ + PQR
= (P’Q’ + PQ)R + (P’Q+PQ’)R’
= (P⊕Q)’ R + (P⊕Q)R’
= (P⊕Q⊕R)
= (P’Q’ + PQ)R + (P’Q+PQ’)R’
= (P⊕Q)’ R + (P⊕Q)R’
= (P⊕Q⊕R)
Question 4 
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?
2^{n} line to 1 line  
2^{n+1} line to 1 line
 
2^{n1} line to 1 line
 
2^{n2} line to 1 line 
Question 4 Explanation:
Both true and complement forms of all variables are necessary to implement any function of n variables.
A 2^{n} X 1 multiplexer can implement any function of n variables. As n variables are given to select lines, so that true and complement forms of all variables get generated inside the MUX.
As one inverter is available, we can generate complement of one variable outside of the Multiplexer. And remaining (n1) variables are given to select lines. With this we have true and complement form of all n variables.
So, the answer is 2^{n1} X 1 MUX.
A 2^{n} X 1 multiplexer can implement any function of n variables. As n variables are given to select lines, so that true and complement forms of all variables get generated inside the MUX.
As one inverter is available, we can generate complement of one variable outside of the Multiplexer. And remaining (n1) variables are given to select lines. With this we have true and complement form of all n variables.
So, the answer is 2^{n1} X 1 MUX.
Question 5 
X1 = b, X2 = 0, X3 = a  
X1 = b, X2 = 1, X3 = b  
X1 = a, X2 = b, X3 = 1  
X1 = a, X2 = 0, X3 = b

Question 5 Explanation:
F = (bX1' + aX1)X3 + X2X3'
If we put
X1 = b
X2 = 0
X3 = a
Then we get,
F = ab
If we put
X1 = b
X2 = 0
X3 = a
Then we get,
F = ab
Question 6 
Question 6 Explanation:
f = yx + y’ (zy’+z’x)
= xy + zy’ + y’z’x
= x(y+y’z’) + zy’
= x(y+z’) + y’z
= xy + xz’ + y’z
= xy + zy’ + y’z’x
= x(y+y’z’) + zy’
= x(y+z’) + y’z
= xy + xz’ + y’z
Question 7 
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2variable Boolean function f = T + R, without using any additional hardware?
R to X, 1 to Y, T to Z
 
T to X, R to Y, T to Z
 
T to X, R to Y, 0 to Z
 
R to X, 0 to Y, T to Z

Question 7 Explanation:
Given,
f = z'x + zy
Put z=T, x=R, y=1 in f
f = T'R + T = (T+T') (R+T) = T+R
Hence, correct option is (A).
f = z'x + zy
Put z=T, x=R, y=1 in f
f = T'R + T = (T+T') (R+T) = T+R
Hence, correct option is (A).
Question 8 
What is the minimum size of ROM required to store the complete truth table of an 8bit × 8bit multiplier?
32 K × 16 bits  
64 K × 16 bits  
16 K × 32 bits  
64 K × 32 bits 
Question 8 Explanation:
Input: 2 lines, 8 bits each
Possible combination in ROM = (2^{8} × (2^{8}) [size of truth table]
= 2^{16}
= 64 KB
= 64 K ×16 bits
Possible combination in ROM = (2^{8} × (2^{8}) [size of truth table]
= 2^{16}
= 64 KB
= 64 K ×16 bits
Question 9 
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
Θ (1)
 
Θ (log n)  
Θ (n)
 
Θ (n^{2}) 
Question 9 Explanation:
Each bit in Multiplier is ANDed with a bit in Multiplicand which produce n nbit numbers. The multiplication takes n units of time. The n nbit numbers are added by using (n1) nbit adders. The time taken by (n1) nbit adders is k*(n1) units.
The total time is n+knk = Θ(n)
The total time is n+knk = Θ(n)
Question 10 
xyz'  
xy+z  
x+y  
None of the above 
Question 10 Explanation:
F = (A'A_{0}'10 + A'A_{0}'11 + A'A_{0}'12 + A_{1}A_{0}13) EN
F = (xyz' + xyz + y'zy + zy')z'
= (xyz' + xyz + y'z(y+1))z'
= (xyz' + xyz + y'z)z'
= (xy(z+z') + y'z)z'
= (xy + y'z)z'
= (xyz' + y'zz')
= (xyz')
F = (xyz' + xyz + y'zy + zy')z'
= (xyz' + xyz + y'z(y+1))z'
= (xyz' + xyz + y'z)z'
= (xy(z+z') + y'z)z'
= (xy + y'z)z'
= (xyz' + y'zz')
= (xyz')
Question 11 
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
On^{2}  
O(n)  
O(log n)  
O(1) 
Question 11 Explanation:
Total no. of gates being used for 'n' bit multiplication in an array multiplier (n*n) = (2n1)
Total delay = 1 * 2n  1 = O(2n  1) = n
Total delay = 1 * 2n  1 = O(2n  1) = n
Question 12 
A multiplexor with a 4 bit data select input is a
4:1 multiplexor  
2:1 multiplexor  
16:1 multiplexor  
8:1 multiplexor

Question 12 Explanation:
For 'n' bit data it selects 2^{n} : 1 input
For 4 bit data it selects 2^{4} : 1 = 16: 1 input
For 4 bit data it selects 2^{4} : 1 = 16: 1 input
There are 14 questions to complete.