## Pipeling

Question 1 |

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.
The number of clock cycles required for completion of execution of the sequence of instructions is ___________.

219 | |

220 | |

221 | |

222 |

Question 1 Explanation:

Total Instruction = 100

Number of stages = 5

We know in a normal pipeline with k-stages time taken for n-instructions = k+n-1 clock cycles.

So, in normal case total cycles = 100 +5 -1 = 104 cycles

But in this question it is given that PO stage of 40 instructions takes 3 cycles, 35 instructions takes 2 cycles and 25 instructions takes 1 cycle. It is also given that all other stages take one clock cycle in all the 100 instructions.

PO stage of 40 instructions takes 3 cycles so these instructions will cause 2 stall cycle each, PO stage of 35 instructions takes 2 cycles so these instructions will cause 1 stall cycle each, But the 25 instruction whose PO stage takes 1 cycle, there are no stall cycles for these.

So, extra stall cycles = 40*2 + 35*1 = 80+35 = 115 cycles. So, total clock cycles = 104 + 115 = 219

Number of stages = 5

We know in a normal pipeline with k-stages time taken for n-instructions = k+n-1 clock cycles.

So, in normal case total cycles = 100 +5 -1 = 104 cycles

But in this question it is given that PO stage of 40 instructions takes 3 cycles, 35 instructions takes 2 cycles and 25 instructions takes 1 cycle. It is also given that all other stages take one clock cycle in all the 100 instructions.

PO stage of 40 instructions takes 3 cycles so these instructions will cause 2 stall cycle each, PO stage of 35 instructions takes 2 cycles so these instructions will cause 1 stall cycle each, But the 25 instruction whose PO stage takes 1 cycle, there are no stall cycles for these.

So, extra stall cycles = 40*2 + 35*1 = 80+35 = 115 cycles. So, total clock cycles = 104 + 115 = 219

Question 2 |

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.

3.2 | |

3.3 | |

3.4 | |

3.5 |

Question 2 Explanation:

Given that the processor clock rate = 2.5 GHz, the processor takes 2.5 G cycles in one second.

Time taken to complete one cycle = (1 / 2.5 G) seconds

Since it is given that average number of cycles per instruction = 4, the time taken for completing one instruction = (4 / 2.5 G) = 1.6 ns

In the pipelined case we know in the ideal case CPI = 1, and the clock speed = 2 GHz.

Time taken for one instruction in the pipelined case = (1 / 2 G) = 0.5 ns

Speedup = 1.6/0.5 = 3.2

Time taken to complete one cycle = (1 / 2.5 G) seconds

Since it is given that average number of cycles per instruction = 4, the time taken for completing one instruction = (4 / 2.5 G) = 1.6 ns

In the pipelined case we know in the ideal case CPI = 1, and the clock speed = 2 GHz.

Time taken for one instruction in the pipelined case = (1 / 2 G) = 0.5 ns

Speedup = 1.6/0.5 = 3.2

There are 2 questions to complete.