Pipeliniing and addressing modes

Question 1
 
A
R1 → R3
R2 → M[100]
B
M[100] → R2
R1 → R2
R1 → R3
C
R1 → M[100]
R2 → R3
D
R1 → R2
R1 → R3
R1 → M[100]
       Computer Organization       Pipeliniing and addressing modes       Gate 2004-IT
Question 1 Explanation: 
Data forwarding means if CPU writes to a memory location and subsequently reads from the same memory location, the second instruction can fetch the value directly from the register used to do write than waiting for the memory. So, this increses the performance.
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