SequentialCircuits
Question 1 
Consider the sequential circuit shown in the figure, where both flipflops used are positive edgetriggered D flipflops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2  
3  
4  
5 
Now lets draw characteristic table,
D_{1} = Q_{0}
D_{0} = in
Question 2 
Consider a combination of T and D flipflops connected as shown below. The output of the D flipflop is connected to the input of the T flipflop and the output of the T flipflop is connected to the input of the D flipflop.
Initially, both Q_{0} and Q_{1} are set to 1 (before the 1^{st} clock cycle). The outputs
Question 3 
The next state table of a 2bit saturating upcounter is given below.
The counter is built as a synchronous sequential circuit using T flipflops. The expressions for T_{1} and T_{0} are
By using above excitation table,
Question 4 
We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK ﬂipﬂops required to implement this counter is __________.
4  
5  
6  
7 
There are 3 transitions from 0.
Hence ⌈log_{2}^{3}⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 5 
0, 1, 3, 7, 15, 14, 12, 8, 0  
0, 1, 3, 5, 7, 9, 11, 13, 15, 0  
0, 2, 4, 6, 8, 10, 12, 14, 0  
0, 8, 12, 14, 15, 7, 3, 1, 0 
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 6 
A positive edgetriggered D flipflop is connected to a positive edgetriggered JK flipflop as follows. The Q output of the D flipflop is connected to both the J and K inputs of the JK flipflop, while the Q output of the JK flipflop is connected to the input of the D flipflop. Initially, the output of the D flipflop is set to logic one and the output of the JK flipflop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flipflop when the flipflops are connected to a freerunning common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the stateholding mode of the JK flipflop. Both the flipflops have nonzero propagation delays.
0110110...  
0100100...  
011101110...  
011001100...

The characteristic equations are
Q_{DN}=D=Q_{JK}
The state table and state transition diagram are as follows:
Consider Q_{D}Q_{JK}=10 as initial state because in the options Q_{JK}=0 is the initial state of JK flipflop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 7 
2  
3  
4  
5 
00
00
01
01
10
10
11
11
In the above sequence two flipflop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
Now and every count is unique, occuring only once.
So finally 3flip flops is required.
Question 8 
kbit binary up counter.  
kbit binary down counter.  
kbit ring counter.  
kbit Johnson counter. 
A n x 2^{n} decoder is a combinational circuit with only one output line has one and all others (2^{n}1) have zeros.
A nbit binary Counter produces outputs from 0 to 2^{n} i.e 000...00 to 111...11 and repeats.
The n x 2^{n} Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2^{n}  bit ring counter.
Question 9 
9  
8  
512  
258 
The max Mod values is 2n.
So 2^{n} ≥ 258 ⇒ n = 9
Question 10 
3  
4  
5  
6 
So total no. of distinct output (states) are 4.
Question 11 
000  
001  
010  
011 
So, after 010 it moves to 011.
Question 12 
11, 10, 01, 00
 
10, 11, 01, 00  
10, 00, 01, 11  
11, 10, 00, 01

The next four values of Q_{1}Q_{0} are 11, 10, 01, 00.
Question 13 
(x⊕y)’ and x’⊕y’  
(x⊕y)’ and x⊕y  
x⊕y and (x⊕y)’  
x⊕y and x⊕y 
Excitation table of JK:
Question 14 
11, 00  
01, 10  
10, 01  
00, 11 
So, 00 input cause indeterminate state which may lead to oscillation.
Question 15 
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flipflop which produces the final output should be negative edge triggered. because whatever the 2nd flipflop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flipflop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flipflop1 responds at next positive edge.
—> After this flipflop2 responds at next negative edge.
That means flipflop2 produces the same input which is given to flipflop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 16 
000  
001  
010  
101 
Question 17 
Question 18 
134  
133  
124  
123 
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 19 
000 101 111  
101 110 111  
011 101 111  
001 110 111  
None of these 
While filling done in reverse order, all operations are not satisfied.
Question 20 
A line L in a circuit is said to have a stuckat0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuckat1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuckat fault if one or more lines have stuck at faults. The total number of distinct multiple stuckat faults possible in a circuit with N lines is
3^{N}  
3^{N}  1  
2^{N}  1  
2 
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3^{N}. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuckatfaults possible in a circuit with N lines is 3^{N}  1.
Question 21 
1, 0, B  
1, 0, A  
0, 1, B  
0, 1, A 
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 22 
Q = 0, Q' = 1
 
Q = 1, Q' = 0
 
Q = 1, Q' = 1
 
Indeterminate states

Output of a NAND is 1 if at least one of its input is zero.
Question 23 
Q_{2}^{c}
 
Q_{2} + Q_{1}
 
(Q_{1} + Q_{2})^{c}
 
Q_{1} ⊕ Q_{2}

0  2  3  1  0
or
00  10  11  01  00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flipflop,
From state table,
Question 24 
zk  nk = 2. In this case, the output at the kth and all subsequent clock ticks is 10. nk  zk = 2. In this case, the output at the kth and all subsequent clock ticks is 01.What is the minimum number of states required in the state transition graph of the above circuit?
5  
6  
7  
8 
q_{0} ← Number of zeros is one more than number of ones.
q_{1} ← Number of ones is one more than number of zeros.
q_{00} ← Number of zeros is two more than number of ones.
q_{11} ← Number of ones is two more than number of zeros.
Question 25 
1, 0  
1, 1  
0, 0  
0, 1 
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0
Question 26 
Error detection  
Error correction
 
Synchronization  
Slowing down the communications 
Question 27 
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q_{1N} = D_{1}×Q_{0}' = 0⋅Q_{0}' = 0
At second +edge, X is 1 and Q_{0}' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q_{0}' is 0, so output is 0.
Now output never changes back to 1 as Q_{0}' is always 0 and when Q_{0}' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 28 
1,3,4,6,7,5,2  
1,2,5,3,7,6,4  
1,2,7,3,5,6,4  
1,6,5,7,2,3,4 
Question 29 
Theory Explanation is given below. 
Question 30 
faster operation  
ease of avoiding problems due to hazards  
lower hardware requirement  
better noise immunity  
none of the above 
Question 31 
1111 1111 0000 0000  
1111 0000 1111 000  
1111 0001 0011 010  
1010 1010 1010 1010 
So we can draw below table to get the output Q_{3}.
From the above table Q_{3} that is output is 1111 0001 0011 010.
So, answer is (C).