Sequential-Circuits
Question 1 |
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2 | |
3 | |
4 | |
5 |
Question 1 Explanation:
Let,
Now lets draw characteristic table,
D1 = Q0
D0 = in
Now lets draw characteristic table,
D1 = Q0
D0 = in
Question 2 |
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.
Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs
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Question 2 Explanation:
Question 3 |
The next state table of a 2-bit saturating up-counter is given below.
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
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Question 3 Explanation:
By using above excitation table,
Question 4 |
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is __________.
4 | |
5 | |
6 | |
7 |
Question 4 Explanation:
Given sequence is 0-1-0-2-0-3
There are 3 transitions from 0.
Hence ⌈log23⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
There are 3 transitions from 0.
Hence ⌈log23⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 5 |
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
0, 1, 3, 7, 15, 14, 12, 8, 0 | |
0, 1, 3, 5, 7, 9, 11, 13, 15, 0 | |
0, 2, 4, 6, 8, 10, 12, 14, 0 | |
0, 8, 12, 14, 15, 7, 3, 1, 0 |
Question 5 Explanation:
In a Johnson’s counter LSB is complemented and a circular right shift operation has to be done to get the next state.
The state sequence is 0,8,12,14,15,7,3,1,0.
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 6 |
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
0110110... | |
0100100... | |
011101110... | |
011001100...
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Question 6 Explanation:
The circuit for the given data is
The characteristic equations are
QDN=D=QJK
The state table and state transition diagram are as follows:
Consider QDQJK=10 as initial state because in the options QJK=0 is the initial state of JK flip-flop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
The characteristic equations are
QDN=D=QJK
The state table and state transition diagram are as follows:
Consider QDQJK=10 as initial state because in the options QJK=0 is the initial state of JK flip-flop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 7 |
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,…….) is ___________.
2 | |
3 | |
4 | |
5 |
Question 7 Explanation:
Count sequence mentioned is
00
00
01
01
10
10
11
11
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
Now and every count is unique, occuring only once.
So finally 3-flip flops is required.
00
00
01
01
10
10
11
11
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
Now and every count is unique, occuring only once.
So finally 3-flip flops is required.
Question 8 |
Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a
k-bit binary up counter. | |
k-bit binary down counter. | |
k-bit ring counter. | |
k-bit Johnson counter. |
Question 8 Explanation:
A ring counter is a circular shift register with only one flip-flop being set at any particular time and all others are cleared.
A n x 2n decoder is a combinational circuit with only one output line has one and all others (2n-1) have zeros.
A n-bit binary Counter produces outputs from 0 to 2n i.e 000...00 to 111...11 and repeats.
The n x 2n Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2n - bit ring counter.
A n x 2n decoder is a combinational circuit with only one output line has one and all others (2n-1) have zeros.
A n-bit binary Counter produces outputs from 0 to 2n i.e 000...00 to 111...11 and repeats.
The n x 2n Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2n - bit ring counter.
Question 9 |
The minimum number of D flip-flops needed to design a mod-258 counter is
9 | |
8 | |
512 | |
258 |
Question 9 Explanation:
Let n is the number of flip-flops.
The max Mod values is 2n.
So 2n ≥ 258 ⇒ n = 9
The max Mod values is 2n.
So 2n ≥ 258 ⇒ n = 9
Question 10 |
Consider the following circuit involving three D-type flip-flops used in a certail type of counter configuration.
If all the flip-flops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?
If all the flip-flops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?
3 | |
4 | |
5 | |
6 |
Question 10 Explanation:
So total no. of distinct output (states) are 4.
Question 11 |
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?000 | |
001 | |
010 | |
011 |
Question 11 Explanation:
So, after 010 it moves to 011.
Question 12 |
In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0?
11, 10, 01, 00
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10, 11, 01, 00 | |
10, 00, 01, 11 | |
11, 10, 00, 01
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Question 12 Explanation:
The next four values of Q1Q0 are 11, 10, 01, 00.
Question 13 |
Consider the following state diagram and its realization by a JK flip flop
The combinational circuit generates J and K in terms of x, y and Q.
The Boolean expressions for J and K are :
The combinational circuit generates J and K in terms of x, y and Q.
The Boolean expressions for J and K are :
(x⊕y)’ and x’⊕y’ | |
(x⊕y)’ and x⊕y | |
x⊕y and (x⊕y)’ | |
x⊕y and x⊕y |
Question 13 Explanation:
From the given statement:
Excitation table of JK:
Excitation table of JK:
Question 14 |
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?
11, 00 | |
01, 10 | |
10, 01 | |
00, 11 |
Question 14 Explanation:
RS slip-flop using NAND gates.
So, 00 input cause indeterminate state which may lead to oscillation.
So, 00 input cause indeterminate state which may lead to oscillation.
Question 15 |
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?
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Question 15 Explanation:
Duty cycle is the period of time where the signal high, i.e. 1.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 16 |
Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:000 | |
001 | |
010 | |
101 |
Question 16 Explanation:
D2 = q1,
D1= q0 ⊕ q2,
D0=external input
Question 17 |
Consider the following circuit
The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:
The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:
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Question 17 Explanation:
Question 18 |
How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
134 | |
133 | |
124 | |
123 |
Question 18 Explanation:
The 8 bit counter will be 0-255 to move from 10101100 (172) to 1000111 (39).
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 19 |
Which of the following input sequences will always generate a 1 at the output Z at the end of the third cycle?
000 101 111 | |
101 110 111 | |
011 101 111 | |
001 110 111 | |
None of these |
Question 19 Explanation:
While filling done in reverse order, all operations are not satisfied.
Question 20 |
A line L in a circuit is said to have a stuck-at-0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuck-at-1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuck-at fault if one or more lines have stuck at faults. The total number of distinct multiple stuck-at faults possible in a circuit with N lines is
3N | |
3N - 1 | |
2N - 1 | |
2 |
Question 20 Explanation:
Answer should be 3N-1.
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
Question 21 |
The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
1, 0, B | |
1, 0, A | |
0, 1, B | |
0, 1, A |
Question 21 Explanation:
In MUX1, the equation is
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 22 |
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1
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Q = 1, Q' = 0
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Q = 1, Q' = 1
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Indeterminate states
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Question 22 Explanation:
The following circuit and truth table of a cross-couple SR latch with 2 NAND gates.
Output of a NAND is 1 if at least one of its input is zero.
Output of a NAND is 1 if at least one of its input is zero.
Question 23 |
Q2c
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Q2 + Q1
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(Q1 + Q2)c
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Q1 ⊕ Q2
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Question 23 Explanation:
Sequence given is
0 - 2 - 3 - 1 - 0
or
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flip-flop,
From state table,
0 - 2 - 3 - 1 - 0
or
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flip-flop,
From state table,
Question 24 |
A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.
zk - nk = 2. In this case, the output at the k-th and
all subsequent clock ticks is 10.
nk - zk = 2. In this case, the output at the k-th and
all subsequent clock ticks is 01.
What is the minimum number of states required in the state transition graph of the above circuit?5 | |
6 | |
7 | |
8 |
Question 24 Explanation:
Let q is the initial state.
q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
Question 25 |
1, 0 | |
1, 1 | |
0, 0 | |
0, 1 |
Question 25 Explanation:
Here clocks are applied to both flip flops simultaneously.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0
Question 26 |
Start and stop bits do not contain an ‘information’ but are used in serial communication for
Error detection | |
Error correction
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Synchronization | |
Slowing down the communications |
Question 26 Explanation:
The start and stop bits are used to synchronize the serial receivers.
Question 27 |
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Question 27 Explanation:
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q1N = D1×Q0' = 0⋅Q0' = 0
At second +edge, X is 1 and Q0' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q0' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q0' is 0, so output is 0.
Now output never changes back to 1 as Q0' is always 0 and when Q0' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 28 |
1,3,4,6,7,5,2 | |
1,2,5,3,7,6,4 | |
1,2,7,3,5,6,4 | |
1,6,5,7,2,3,4 |
Question 28 Explanation:
Question 29 |
Theory Explanation is given below. |
Question 29 Explanation:
Question 30 |
faster operation | |
ease of avoiding problems due to hazards | |
lower hardware requirement | |
better noise immunity | |
none of the above |
Question 30 Explanation:
In synchronization, there is a less chance of hazards but it can increase the delay. Then the advantage is ease of avoiding problems due to hazards.
Question 31 |
The above circuit produces the output sequence:
1111 1111 0000 0000 | |
1111 0000 1111 000 | |
1111 0001 0011 010 | |
1010 1010 1010 1010 |
Question 31 Explanation:
Let us suppose initially output of all JK flip flop is 1.
So we can draw below table to get the output Q3.
From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).
So we can draw below table to get the output Q3.
From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).
There are 31 questions to complete.