Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
Now lets draw characteristic table,
D1 = Q0
D0 = in
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.
Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs
The next state table of a 2-bit saturating up-counter is given below.
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
By using above excitation table,
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K ﬂip-ﬂops required to implement this counter is __________.
There are 3 transitions from 0.
Hence ⌈log23⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
0, 1, 3, 7, 15, 14, 12, 8, 0
0, 1, 3, 5, 7, 9, 11, 13, 15, 0
0, 2, 4, 6, 8, 10, 12, 14, 0
0, 8, 12, 14, 15, 7, 3, 1, 0
The state sequence is 0,8,12,14,15,7,3,1,0.
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
The characteristic equations are
The state table and state transition diagram are as follows:
Consider QDQJK=10 as initial state because in the options QJK=0 is the initial state of JK flip-flop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
Now and every count is unique, occuring only once.
So finally 3-flip flops is required.
k-bit binary up counter.
k-bit binary down counter.
k-bit ring counter.
k-bit Johnson counter.
A n x 2n decoder is a combinational circuit with only one output line has one and all others (2n-1) have zeros.
A n-bit binary Counter produces outputs from 0 to 2n i.e 000...00 to 111...11 and repeats.
The n x 2n Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2n - bit ring counter.
The max Mod values is 2n.
So 2n ≥ 258 ⇒ n = 9
So total no. of distinct output (states) are 4.
So, after 010 it moves to 011.
11, 10, 01, 00
10, 11, 01, 00
10, 00, 01, 11
11, 10, 00, 01
The next four values of Q1Q0 are 11, 10, 01, 00.
(x⊕y)’ and x’⊕y’
(x⊕y)’ and x⊕y
x⊕y and (x⊕y)’
x⊕y and x⊕y
Excitation table of JK:
So, 00 input cause indeterminate state which may lead to oscillation.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
None of these
While filling done in reverse order, all operations are not satisfied.
A line L in a circuit is said to have a stuck-at-0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuck-at-1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuck-at fault if one or more lines have stuck at faults. The total number of distinct multiple stuck-at faults possible in a circuit with N lines is
3N - 1
2N - 1
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
1, 0, B
1, 0, A
0, 1, B
0, 1, A
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
∴ Option (D) is correct.
Q = 0, Q' = 1
Q = 1, Q' = 0
Q = 1, Q' = 1
Truth table for the SR latch by cross coupling two NAND gates is
So, Answer is Option (D).
Q2 + Q1
(Q1 + Q2)c
Q1 ⊕ Q2
0 - 2 - 3 - 1 - 0
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flip-flop,
From state table,
q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0
Slowing down the communications
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q1N = D1×Q0' = 0⋅Q0' = 0
At second +edge, X is 1 and Q0' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q0' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q0' is 0, so output is 0.
Now output never changes back to 1 as Q0' is always 0 and when Q0' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Theory Explanation is given below.
ease of avoiding problems due to hazards
lower hardware requirement
better noise immunity
none of the above
1111 1111 0000 0000
1111 0000 1111 000
1111 0001 0011 010
1010 1010 1010 1010
So we can draw below table to get the output Q3.
From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).